1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * NetChip 2280 high/full speed USB device controller. 4*4882a593Smuzhiyun * Unlike many such controllers, this one talks PCI. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) 7*4882a593Smuzhiyun * Copyright (C) 2003 David Brownell 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 10*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 11*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 12*4882a593Smuzhiyun * (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 20*4882a593Smuzhiyun * along with this program; if not, write to the Free Software 21*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __LINUX_USB_NET2280_H 25*4882a593Smuzhiyun #define __LINUX_USB_NET2280_H 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* NET2280 MEMORY MAPPED REGISTERS 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * The register layout came from the chip documentation, and the bit 32*4882a593Smuzhiyun * number definitions were extracted from chip specification. 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * Use the shift operator ('<<') to build bit masks, with readl/writel 35*4882a593Smuzhiyun * to access the registers through PCI. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* main registers, BAR0 + 0x0000 */ 39*4882a593Smuzhiyun struct net2280_regs { 40*4882a593Smuzhiyun /* offset 0x0000 */ 41*4882a593Smuzhiyun u32 devinit; 42*4882a593Smuzhiyun #define LOCAL_CLOCK_FREQUENCY 8 43*4882a593Smuzhiyun #define FORCE_PCI_RESET 7 44*4882a593Smuzhiyun #define PCI_ID 6 45*4882a593Smuzhiyun #define PCI_ENABLE 5 46*4882a593Smuzhiyun #define FIFO_SOFT_RESET 4 47*4882a593Smuzhiyun #define CFG_SOFT_RESET 3 48*4882a593Smuzhiyun #define PCI_SOFT_RESET 2 49*4882a593Smuzhiyun #define USB_SOFT_RESET 1 50*4882a593Smuzhiyun #define M8051_RESET 0 51*4882a593Smuzhiyun u32 eectl; 52*4882a593Smuzhiyun #define EEPROM_ADDRESS_WIDTH 23 53*4882a593Smuzhiyun #define EEPROM_CHIP_SELECT_ACTIVE 22 54*4882a593Smuzhiyun #define EEPROM_PRESENT 21 55*4882a593Smuzhiyun #define EEPROM_VALID 20 56*4882a593Smuzhiyun #define EEPROM_BUSY 19 57*4882a593Smuzhiyun #define EEPROM_CHIP_SELECT_ENABLE 18 58*4882a593Smuzhiyun #define EEPROM_BYTE_READ_START 17 59*4882a593Smuzhiyun #define EEPROM_BYTE_WRITE_START 16 60*4882a593Smuzhiyun #define EEPROM_READ_DATA 8 61*4882a593Smuzhiyun #define EEPROM_WRITE_DATA 0 62*4882a593Smuzhiyun u32 eeclkfreq; 63*4882a593Smuzhiyun u32 _unused0; 64*4882a593Smuzhiyun /* offset 0x0010 */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun u32 pciirqenb0; /* interrupt PCI master ... */ 67*4882a593Smuzhiyun #define SETUP_PACKET_INTERRUPT_ENABLE 7 68*4882a593Smuzhiyun #define ENDPOINT_F_INTERRUPT_ENABLE 6 69*4882a593Smuzhiyun #define ENDPOINT_E_INTERRUPT_ENABLE 5 70*4882a593Smuzhiyun #define ENDPOINT_D_INTERRUPT_ENABLE 4 71*4882a593Smuzhiyun #define ENDPOINT_C_INTERRUPT_ENABLE 3 72*4882a593Smuzhiyun #define ENDPOINT_B_INTERRUPT_ENABLE 2 73*4882a593Smuzhiyun #define ENDPOINT_A_INTERRUPT_ENABLE 1 74*4882a593Smuzhiyun #define ENDPOINT_0_INTERRUPT_ENABLE 0 75*4882a593Smuzhiyun u32 pciirqenb1; 76*4882a593Smuzhiyun #define PCI_INTERRUPT_ENABLE 31 77*4882a593Smuzhiyun #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 78*4882a593Smuzhiyun #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 79*4882a593Smuzhiyun #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 80*4882a593Smuzhiyun #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 81*4882a593Smuzhiyun #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 82*4882a593Smuzhiyun #define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18 83*4882a593Smuzhiyun #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 84*4882a593Smuzhiyun #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 85*4882a593Smuzhiyun #define GPIO_INTERRUPT_ENABLE 13 86*4882a593Smuzhiyun #define DMA_D_INTERRUPT_ENABLE 12 87*4882a593Smuzhiyun #define DMA_C_INTERRUPT_ENABLE 11 88*4882a593Smuzhiyun #define DMA_B_INTERRUPT_ENABLE 10 89*4882a593Smuzhiyun #define DMA_A_INTERRUPT_ENABLE 9 90*4882a593Smuzhiyun #define EEPROM_DONE_INTERRUPT_ENABLE 8 91*4882a593Smuzhiyun #define VBUS_INTERRUPT_ENABLE 7 92*4882a593Smuzhiyun #define CONTROL_STATUS_INTERRUPT_ENABLE 6 93*4882a593Smuzhiyun #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 94*4882a593Smuzhiyun #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 95*4882a593Smuzhiyun #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 96*4882a593Smuzhiyun #define RESUME_INTERRUPT_ENABLE 1 97*4882a593Smuzhiyun #define SOF_INTERRUPT_ENABLE 0 98*4882a593Smuzhiyun u32 cpu_irqenb0; /* ... or onboard 8051 */ 99*4882a593Smuzhiyun #define SETUP_PACKET_INTERRUPT_ENABLE 7 100*4882a593Smuzhiyun #define ENDPOINT_F_INTERRUPT_ENABLE 6 101*4882a593Smuzhiyun #define ENDPOINT_E_INTERRUPT_ENABLE 5 102*4882a593Smuzhiyun #define ENDPOINT_D_INTERRUPT_ENABLE 4 103*4882a593Smuzhiyun #define ENDPOINT_C_INTERRUPT_ENABLE 3 104*4882a593Smuzhiyun #define ENDPOINT_B_INTERRUPT_ENABLE 2 105*4882a593Smuzhiyun #define ENDPOINT_A_INTERRUPT_ENABLE 1 106*4882a593Smuzhiyun #define ENDPOINT_0_INTERRUPT_ENABLE 0 107*4882a593Smuzhiyun u32 cpu_irqenb1; 108*4882a593Smuzhiyun #define CPU_INTERRUPT_ENABLE 31 109*4882a593Smuzhiyun #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 110*4882a593Smuzhiyun #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 111*4882a593Smuzhiyun #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 112*4882a593Smuzhiyun #define PCI_INTA_INTERRUPT_ENABLE 24 113*4882a593Smuzhiyun #define PCI_PME_INTERRUPT_ENABLE 23 114*4882a593Smuzhiyun #define PCI_SERR_INTERRUPT_ENABLE 22 115*4882a593Smuzhiyun #define PCI_PERR_INTERRUPT_ENABLE 21 116*4882a593Smuzhiyun #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 117*4882a593Smuzhiyun #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 118*4882a593Smuzhiyun #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 119*4882a593Smuzhiyun #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 120*4882a593Smuzhiyun #define GPIO_INTERRUPT_ENABLE 13 121*4882a593Smuzhiyun #define DMA_D_INTERRUPT_ENABLE 12 122*4882a593Smuzhiyun #define DMA_C_INTERRUPT_ENABLE 11 123*4882a593Smuzhiyun #define DMA_B_INTERRUPT_ENABLE 10 124*4882a593Smuzhiyun #define DMA_A_INTERRUPT_ENABLE 9 125*4882a593Smuzhiyun #define EEPROM_DONE_INTERRUPT_ENABLE 8 126*4882a593Smuzhiyun #define VBUS_INTERRUPT_ENABLE 7 127*4882a593Smuzhiyun #define CONTROL_STATUS_INTERRUPT_ENABLE 6 128*4882a593Smuzhiyun #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 129*4882a593Smuzhiyun #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 130*4882a593Smuzhiyun #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 131*4882a593Smuzhiyun #define RESUME_INTERRUPT_ENABLE 1 132*4882a593Smuzhiyun #define SOF_INTERRUPT_ENABLE 0 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* offset 0x0020 */ 135*4882a593Smuzhiyun u32 _unused1; 136*4882a593Smuzhiyun u32 usbirqenb1; 137*4882a593Smuzhiyun #define USB_INTERRUPT_ENABLE 31 138*4882a593Smuzhiyun #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 139*4882a593Smuzhiyun #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 140*4882a593Smuzhiyun #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 141*4882a593Smuzhiyun #define PCI_INTA_INTERRUPT_ENABLE 24 142*4882a593Smuzhiyun #define PCI_PME_INTERRUPT_ENABLE 23 143*4882a593Smuzhiyun #define PCI_SERR_INTERRUPT_ENABLE 22 144*4882a593Smuzhiyun #define PCI_PERR_INTERRUPT_ENABLE 21 145*4882a593Smuzhiyun #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 146*4882a593Smuzhiyun #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 147*4882a593Smuzhiyun #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 148*4882a593Smuzhiyun #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 149*4882a593Smuzhiyun #define GPIO_INTERRUPT_ENABLE 13 150*4882a593Smuzhiyun #define DMA_D_INTERRUPT_ENABLE 12 151*4882a593Smuzhiyun #define DMA_C_INTERRUPT_ENABLE 11 152*4882a593Smuzhiyun #define DMA_B_INTERRUPT_ENABLE 10 153*4882a593Smuzhiyun #define DMA_A_INTERRUPT_ENABLE 9 154*4882a593Smuzhiyun #define EEPROM_DONE_INTERRUPT_ENABLE 8 155*4882a593Smuzhiyun #define VBUS_INTERRUPT_ENABLE 7 156*4882a593Smuzhiyun #define CONTROL_STATUS_INTERRUPT_ENABLE 6 157*4882a593Smuzhiyun #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 158*4882a593Smuzhiyun #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 159*4882a593Smuzhiyun #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 160*4882a593Smuzhiyun #define RESUME_INTERRUPT_ENABLE 1 161*4882a593Smuzhiyun #define SOF_INTERRUPT_ENABLE 0 162*4882a593Smuzhiyun u32 irqstat0; 163*4882a593Smuzhiyun #define INTA_ASSERTED 12 164*4882a593Smuzhiyun #define SETUP_PACKET_INTERRUPT 7 165*4882a593Smuzhiyun #define ENDPOINT_F_INTERRUPT 6 166*4882a593Smuzhiyun #define ENDPOINT_E_INTERRUPT 5 167*4882a593Smuzhiyun #define ENDPOINT_D_INTERRUPT 4 168*4882a593Smuzhiyun #define ENDPOINT_C_INTERRUPT 3 169*4882a593Smuzhiyun #define ENDPOINT_B_INTERRUPT 2 170*4882a593Smuzhiyun #define ENDPOINT_A_INTERRUPT 1 171*4882a593Smuzhiyun #define ENDPOINT_0_INTERRUPT 0 172*4882a593Smuzhiyun #define USB3380_IRQSTAT0_EP_INTR_MASK_IN (0xF << 17) 173*4882a593Smuzhiyun #define USB3380_IRQSTAT0_EP_INTR_MASK_OUT (0xF << 1) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun u32 irqstat1; 176*4882a593Smuzhiyun #define POWER_STATE_CHANGE_INTERRUPT 27 177*4882a593Smuzhiyun #define PCI_ARBITER_TIMEOUT_INTERRUPT 26 178*4882a593Smuzhiyun #define PCI_PARITY_ERROR_INTERRUPT 25 179*4882a593Smuzhiyun #define PCI_INTA_INTERRUPT 24 180*4882a593Smuzhiyun #define PCI_PME_INTERRUPT 23 181*4882a593Smuzhiyun #define PCI_SERR_INTERRUPT 22 182*4882a593Smuzhiyun #define PCI_PERR_INTERRUPT 21 183*4882a593Smuzhiyun #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20 184*4882a593Smuzhiyun #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19 185*4882a593Smuzhiyun #define PCI_RETRY_ABORT_INTERRUPT 17 186*4882a593Smuzhiyun #define PCI_MASTER_CYCLE_DONE_INTERRUPT 16 187*4882a593Smuzhiyun #define SOF_DOWN_INTERRUPT 14 188*4882a593Smuzhiyun #define GPIO_INTERRUPT 13 189*4882a593Smuzhiyun #define DMA_D_INTERRUPT 12 190*4882a593Smuzhiyun #define DMA_C_INTERRUPT 11 191*4882a593Smuzhiyun #define DMA_B_INTERRUPT 10 192*4882a593Smuzhiyun #define DMA_A_INTERRUPT 9 193*4882a593Smuzhiyun #define EEPROM_DONE_INTERRUPT 8 194*4882a593Smuzhiyun #define VBUS_INTERRUPT 7 195*4882a593Smuzhiyun #define CONTROL_STATUS_INTERRUPT 6 196*4882a593Smuzhiyun #define ROOT_PORT_RESET_INTERRUPT 4 197*4882a593Smuzhiyun #define SUSPEND_REQUEST_INTERRUPT 3 198*4882a593Smuzhiyun #define SUSPEND_REQUEST_CHANGE_INTERRUPT 2 199*4882a593Smuzhiyun #define RESUME_INTERRUPT 1 200*4882a593Smuzhiyun #define SOF_INTERRUPT 0 201*4882a593Smuzhiyun /* offset 0x0030 */ 202*4882a593Smuzhiyun u32 idxaddr; 203*4882a593Smuzhiyun u32 idxdata; 204*4882a593Smuzhiyun u32 fifoctl; 205*4882a593Smuzhiyun #define PCI_BASE2_RANGE 16 206*4882a593Smuzhiyun #define IGNORE_FIFO_AVAILABILITY 3 207*4882a593Smuzhiyun #define PCI_BASE2_SELECT 2 208*4882a593Smuzhiyun #define FIFO_CONFIGURATION_SELECT 0 209*4882a593Smuzhiyun u32 _unused2; 210*4882a593Smuzhiyun /* offset 0x0040 */ 211*4882a593Smuzhiyun u32 memaddr; 212*4882a593Smuzhiyun #define START 28 213*4882a593Smuzhiyun #define DIRECTION 27 214*4882a593Smuzhiyun #define FIFO_DIAGNOSTIC_SELECT 24 215*4882a593Smuzhiyun #define MEMORY_ADDRESS 0 216*4882a593Smuzhiyun u32 memdata0; 217*4882a593Smuzhiyun u32 memdata1; 218*4882a593Smuzhiyun u32 _unused3; 219*4882a593Smuzhiyun /* offset 0x0050 */ 220*4882a593Smuzhiyun u32 gpioctl; 221*4882a593Smuzhiyun #define GPIO3_LED_SELECT 12 222*4882a593Smuzhiyun #define GPIO3_INTERRUPT_ENABLE 11 223*4882a593Smuzhiyun #define GPIO2_INTERRUPT_ENABLE 10 224*4882a593Smuzhiyun #define GPIO1_INTERRUPT_ENABLE 9 225*4882a593Smuzhiyun #define GPIO0_INTERRUPT_ENABLE 8 226*4882a593Smuzhiyun #define GPIO3_OUTPUT_ENABLE 7 227*4882a593Smuzhiyun #define GPIO2_OUTPUT_ENABLE 6 228*4882a593Smuzhiyun #define GPIO1_OUTPUT_ENABLE 5 229*4882a593Smuzhiyun #define GPIO0_OUTPUT_ENABLE 4 230*4882a593Smuzhiyun #define GPIO3_DATA 3 231*4882a593Smuzhiyun #define GPIO2_DATA 2 232*4882a593Smuzhiyun #define GPIO1_DATA 1 233*4882a593Smuzhiyun #define GPIO0_DATA 0 234*4882a593Smuzhiyun u32 gpiostat; 235*4882a593Smuzhiyun #define GPIO3_INTERRUPT 3 236*4882a593Smuzhiyun #define GPIO2_INTERRUPT 2 237*4882a593Smuzhiyun #define GPIO1_INTERRUPT 1 238*4882a593Smuzhiyun #define GPIO0_INTERRUPT 0 239*4882a593Smuzhiyun } __attribute__ ((packed)); 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun /* usb control, BAR0 + 0x0080 */ 242*4882a593Smuzhiyun struct net2280_usb_regs { 243*4882a593Smuzhiyun /* offset 0x0080 */ 244*4882a593Smuzhiyun u32 stdrsp; 245*4882a593Smuzhiyun #define STALL_UNSUPPORTED_REQUESTS 31 246*4882a593Smuzhiyun #define SET_TEST_MODE 16 247*4882a593Smuzhiyun #define GET_OTHER_SPEED_CONFIGURATION 15 248*4882a593Smuzhiyun #define GET_DEVICE_QUALIFIER 14 249*4882a593Smuzhiyun #define SET_ADDRESS 13 250*4882a593Smuzhiyun #define ENDPOINT_SET_CLEAR_HALT 12 251*4882a593Smuzhiyun #define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11 252*4882a593Smuzhiyun #define GET_STRING_DESCRIPTOR_2 10 253*4882a593Smuzhiyun #define GET_STRING_DESCRIPTOR_1 9 254*4882a593Smuzhiyun #define GET_STRING_DESCRIPTOR_0 8 255*4882a593Smuzhiyun #define GET_SET_INTERFACE 6 256*4882a593Smuzhiyun #define GET_SET_CONFIGURATION 5 257*4882a593Smuzhiyun #define GET_CONFIGURATION_DESCRIPTOR 4 258*4882a593Smuzhiyun #define GET_DEVICE_DESCRIPTOR 3 259*4882a593Smuzhiyun #define GET_ENDPOINT_STATUS 2 260*4882a593Smuzhiyun #define GET_INTERFACE_STATUS 1 261*4882a593Smuzhiyun #define GET_DEVICE_STATUS 0 262*4882a593Smuzhiyun u32 prodvendid; 263*4882a593Smuzhiyun #define PRODUCT_ID 16 264*4882a593Smuzhiyun #define VENDOR_ID 0 265*4882a593Smuzhiyun u32 relnum; 266*4882a593Smuzhiyun u32 usbctl; 267*4882a593Smuzhiyun #define SERIAL_NUMBER_INDEX 16 268*4882a593Smuzhiyun #define PRODUCT_ID_STRING_ENABLE 13 269*4882a593Smuzhiyun #define VENDOR_ID_STRING_ENABLE 12 270*4882a593Smuzhiyun #define USB_ROOT_PORT_WAKEUP_ENABLE 11 271*4882a593Smuzhiyun #define VBUS_PIN 10 272*4882a593Smuzhiyun #define TIMED_DISCONNECT 9 273*4882a593Smuzhiyun #define SUSPEND_IMMEDIATELY 7 274*4882a593Smuzhiyun #define SELF_POWERED_USB_DEVICE 6 275*4882a593Smuzhiyun #define REMOTE_WAKEUP_SUPPORT 5 276*4882a593Smuzhiyun #define PME_POLARITY 4 277*4882a593Smuzhiyun #define USB_DETECT_ENABLE 3 278*4882a593Smuzhiyun #define PME_WAKEUP_ENABLE 2 279*4882a593Smuzhiyun #define DEVICE_REMOTE_WAKEUP_ENABLE 1 280*4882a593Smuzhiyun #define SELF_POWERED_STATUS 0 281*4882a593Smuzhiyun /* offset 0x0090 */ 282*4882a593Smuzhiyun u32 usbstat; 283*4882a593Smuzhiyun #define HIGH_SPEED 7 284*4882a593Smuzhiyun #define FULL_SPEED 6 285*4882a593Smuzhiyun #define GENERATE_RESUME 5 286*4882a593Smuzhiyun #define GENERATE_DEVICE_REMOTE_WAKEUP 4 287*4882a593Smuzhiyun u32 xcvrdiag; 288*4882a593Smuzhiyun #define FORCE_HIGH_SPEED_MODE 31 289*4882a593Smuzhiyun #define FORCE_FULL_SPEED_MODE 30 290*4882a593Smuzhiyun #define USB_TEST_MODE 24 291*4882a593Smuzhiyun #define LINE_STATE 16 292*4882a593Smuzhiyun #define TRANSCEIVER_OPERATION_MODE 2 293*4882a593Smuzhiyun #define TRANSCEIVER_SELECT 1 294*4882a593Smuzhiyun #define TERMINATION_SELECT 0 295*4882a593Smuzhiyun u32 setup0123; 296*4882a593Smuzhiyun u32 setup4567; 297*4882a593Smuzhiyun /* offset 0x0090 */ 298*4882a593Smuzhiyun u32 _unused0; 299*4882a593Smuzhiyun u32 ouraddr; 300*4882a593Smuzhiyun #define FORCE_IMMEDIATE 7 301*4882a593Smuzhiyun #define OUR_USB_ADDRESS 0 302*4882a593Smuzhiyun u32 ourconfig; 303*4882a593Smuzhiyun } __attribute__ ((packed)); 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun /* pci control, BAR0 + 0x0100 */ 306*4882a593Smuzhiyun struct net2280_pci_regs { 307*4882a593Smuzhiyun /* offset 0x0100 */ 308*4882a593Smuzhiyun u32 pcimstctl; 309*4882a593Smuzhiyun #define PCI_ARBITER_PARK_SELECT 13 310*4882a593Smuzhiyun #define PCI_MULTI LEVEL_ARBITER 12 311*4882a593Smuzhiyun #define PCI_RETRY_ABORT_ENABLE 11 312*4882a593Smuzhiyun #define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10 313*4882a593Smuzhiyun #define DMA_READ_MULTIPLE_ENABLE 9 314*4882a593Smuzhiyun #define DMA_READ_LINE_ENABLE 8 315*4882a593Smuzhiyun #define PCI_MASTER_COMMAND_SELECT 6 316*4882a593Smuzhiyun #define MEM_READ_OR_WRITE 0 317*4882a593Smuzhiyun #define IO_READ_OR_WRITE 1 318*4882a593Smuzhiyun #define CFG_READ_OR_WRITE 2 319*4882a593Smuzhiyun #define PCI_MASTER_START 5 320*4882a593Smuzhiyun #define PCI_MASTER_READ_WRITE 4 321*4882a593Smuzhiyun #define PCI_MASTER_WRITE 0 322*4882a593Smuzhiyun #define PCI_MASTER_READ 1 323*4882a593Smuzhiyun #define PCI_MASTER_BYTE_WRITE_ENABLES 0 324*4882a593Smuzhiyun u32 pcimstaddr; 325*4882a593Smuzhiyun u32 pcimstdata; 326*4882a593Smuzhiyun u32 pcimststat; 327*4882a593Smuzhiyun #define PCI_ARBITER_CLEAR 2 328*4882a593Smuzhiyun #define PCI_EXTERNAL_ARBITER 1 329*4882a593Smuzhiyun #define PCI_HOST_MODE 0 330*4882a593Smuzhiyun } __attribute__ ((packed)); 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun /* dma control, BAR0 + 0x0180 ... array of four structs like this, 333*4882a593Smuzhiyun * for channels 0..3. see also struct net2280_dma: descriptor 334*4882a593Smuzhiyun * that can be loaded into some of these registers. 335*4882a593Smuzhiyun */ 336*4882a593Smuzhiyun struct net2280_dma_regs { /* [11.7] */ 337*4882a593Smuzhiyun /* offset 0x0180, 0x01a0, 0x01c0, 0x01e0, */ 338*4882a593Smuzhiyun u32 dmactl; 339*4882a593Smuzhiyun #define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25 340*4882a593Smuzhiyun #define DMA_CLEAR_COUNT_ENABLE 21 341*4882a593Smuzhiyun #define DESCRIPTOR_POLLING_RATE 19 342*4882a593Smuzhiyun #define POLL_CONTINUOUS 0 343*4882a593Smuzhiyun #define POLL_1_USEC 1 344*4882a593Smuzhiyun #define POLL_100_USEC 2 345*4882a593Smuzhiyun #define POLL_1_MSEC 3 346*4882a593Smuzhiyun #define DMA_VALID_BIT_POLLING_ENABLE 18 347*4882a593Smuzhiyun #define DMA_VALID_BIT_ENABLE 17 348*4882a593Smuzhiyun #define DMA_SCATTER_GATHER_ENABLE 16 349*4882a593Smuzhiyun #define DMA_OUT_AUTO_START_ENABLE 4 350*4882a593Smuzhiyun #define DMA_PREEMPT_ENABLE 3 351*4882a593Smuzhiyun #define DMA_FIFO_VALIDATE 2 352*4882a593Smuzhiyun #define DMA_ENABLE 1 353*4882a593Smuzhiyun #define DMA_ADDRESS_HOLD 0 354*4882a593Smuzhiyun u32 dmastat; 355*4882a593Smuzhiyun #define DMA_ABORT_DONE_INTERRUPT 27 356*4882a593Smuzhiyun #define DMA_SCATTER_GATHER_DONE_INTERRUPT 25 357*4882a593Smuzhiyun #define DMA_TRANSACTION_DONE_INTERRUPT 24 358*4882a593Smuzhiyun #define DMA_ABORT 1 359*4882a593Smuzhiyun #define DMA_START 0 360*4882a593Smuzhiyun u32 _unused0[2]; 361*4882a593Smuzhiyun /* offset 0x0190, 0x01b0, 0x01d0, 0x01f0, */ 362*4882a593Smuzhiyun u32 dmacount; 363*4882a593Smuzhiyun #define VALID_BIT 31 364*4882a593Smuzhiyun #define DMA_DIRECTION 30 365*4882a593Smuzhiyun #define DMA_DONE_INTERRUPT_ENABLE 29 366*4882a593Smuzhiyun #define END_OF_CHAIN 28 367*4882a593Smuzhiyun #define DMA_BYTE_COUNT_MASK ((1<<24)-1) 368*4882a593Smuzhiyun #define DMA_BYTE_COUNT 0 369*4882a593Smuzhiyun u32 dmaaddr; 370*4882a593Smuzhiyun u32 dmadesc; 371*4882a593Smuzhiyun u32 _unused1; 372*4882a593Smuzhiyun } __attribute__ ((packed)); 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun /* dedicated endpoint registers, BAR0 + 0x0200 */ 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun struct net2280_dep_regs { /* [11.8] */ 377*4882a593Smuzhiyun /* offset 0x0200, 0x0210, 0x220, 0x230, 0x240 */ 378*4882a593Smuzhiyun u32 dep_cfg; 379*4882a593Smuzhiyun /* offset 0x0204, 0x0214, 0x224, 0x234, 0x244 */ 380*4882a593Smuzhiyun u32 dep_rsp; 381*4882a593Smuzhiyun u32 _unused[2]; 382*4882a593Smuzhiyun } __attribute__ ((packed)); 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs 385*4882a593Smuzhiyun * like this, for ep0 then the configurable endpoints A..F 386*4882a593Smuzhiyun * ep0 reserved for control; E and F have only 64 bytes of fifo 387*4882a593Smuzhiyun */ 388*4882a593Smuzhiyun struct net2280_ep_regs { /* [11.9] */ 389*4882a593Smuzhiyun /* offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 */ 390*4882a593Smuzhiyun u32 ep_cfg; 391*4882a593Smuzhiyun #define ENDPOINT_BYTE_COUNT 16 392*4882a593Smuzhiyun #define ENDPOINT_ENABLE 10 393*4882a593Smuzhiyun #define ENDPOINT_TYPE 8 394*4882a593Smuzhiyun #define ENDPOINT_DIRECTION 7 395*4882a593Smuzhiyun #define ENDPOINT_NUMBER 0 396*4882a593Smuzhiyun u32 ep_rsp; 397*4882a593Smuzhiyun #define SET_NAK_OUT_PACKETS 15 398*4882a593Smuzhiyun #define SET_EP_HIDE_STATUS_PHASE 14 399*4882a593Smuzhiyun #define SET_EP_FORCE_CRC_ERROR 13 400*4882a593Smuzhiyun #define SET_INTERRUPT_MODE 12 401*4882a593Smuzhiyun #define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11 402*4882a593Smuzhiyun #define SET_NAK_OUT_PACKETS_MODE 10 403*4882a593Smuzhiyun #define SET_ENDPOINT_TOGGLE 9 404*4882a593Smuzhiyun #define SET_ENDPOINT_HALT 8 405*4882a593Smuzhiyun #define CLEAR_NAK_OUT_PACKETS 7 406*4882a593Smuzhiyun #define CLEAR_EP_HIDE_STATUS_PHASE 6 407*4882a593Smuzhiyun #define CLEAR_EP_FORCE_CRC_ERROR 5 408*4882a593Smuzhiyun #define CLEAR_INTERRUPT_MODE 4 409*4882a593Smuzhiyun #define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3 410*4882a593Smuzhiyun #define CLEAR_NAK_OUT_PACKETS_MODE 2 411*4882a593Smuzhiyun #define CLEAR_ENDPOINT_TOGGLE 1 412*4882a593Smuzhiyun #define CLEAR_ENDPOINT_HALT 0 413*4882a593Smuzhiyun u32 ep_irqenb; 414*4882a593Smuzhiyun #define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6 415*4882a593Smuzhiyun #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5 416*4882a593Smuzhiyun #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3 417*4882a593Smuzhiyun #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2 418*4882a593Smuzhiyun #define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1 419*4882a593Smuzhiyun #define DATA_IN_TOKEN_INTERRUPT_ENABLE 0 420*4882a593Smuzhiyun u32 ep_stat; 421*4882a593Smuzhiyun #define FIFO_VALID_COUNT 24 422*4882a593Smuzhiyun #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22 423*4882a593Smuzhiyun #define TIMEOUT 21 424*4882a593Smuzhiyun #define USB_STALL_SENT 20 425*4882a593Smuzhiyun #define USB_IN_NAK_SENT 19 426*4882a593Smuzhiyun #define USB_IN_ACK_RCVD 18 427*4882a593Smuzhiyun #define USB_OUT_PING_NAK_SENT 17 428*4882a593Smuzhiyun #define USB_OUT_ACK_SENT 16 429*4882a593Smuzhiyun #define FIFO_OVERFLOW 13 430*4882a593Smuzhiyun #define FIFO_UNDERFLOW 12 431*4882a593Smuzhiyun #define FIFO_FULL 11 432*4882a593Smuzhiyun #define FIFO_EMPTY 10 433*4882a593Smuzhiyun #define FIFO_FLUSH 9 434*4882a593Smuzhiyun #define SHORT_PACKET_OUT_DONE_INTERRUPT 6 435*4882a593Smuzhiyun #define SHORT_PACKET_TRANSFERRED_INTERRUPT 5 436*4882a593Smuzhiyun #define NAK_OUT_PACKETS 4 437*4882a593Smuzhiyun #define DATA_PACKET_RECEIVED_INTERRUPT 3 438*4882a593Smuzhiyun #define DATA_PACKET_TRANSMITTED_INTERRUPT 2 439*4882a593Smuzhiyun #define DATA_OUT_PING_TOKEN_INTERRUPT 1 440*4882a593Smuzhiyun #define DATA_IN_TOKEN_INTERRUPT 0 441*4882a593Smuzhiyun /* offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 */ 442*4882a593Smuzhiyun u32 ep_avail; 443*4882a593Smuzhiyun u32 ep_data; 444*4882a593Smuzhiyun u32 _unused0[2]; 445*4882a593Smuzhiyun } __attribute__ ((packed)); 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun #endif /* __LINUX_USB_NET2280_H */ 448