1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __LINUX_ULPI_REGS_H 3*4882a593Smuzhiyun #define __LINUX_ULPI_REGS_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Macros for Set and Clear 7*4882a593Smuzhiyun * See ULPI 1.1 specification to find the registers with Set and Clear offsets 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #define ULPI_SET(a) (a + 1) 10*4882a593Smuzhiyun #define ULPI_CLR(a) (a + 2) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Register Map 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define ULPI_VENDOR_ID_LOW 0x00 16*4882a593Smuzhiyun #define ULPI_VENDOR_ID_HIGH 0x01 17*4882a593Smuzhiyun #define ULPI_PRODUCT_ID_LOW 0x02 18*4882a593Smuzhiyun #define ULPI_PRODUCT_ID_HIGH 0x03 19*4882a593Smuzhiyun #define ULPI_FUNC_CTRL 0x04 20*4882a593Smuzhiyun #define ULPI_IFC_CTRL 0x07 21*4882a593Smuzhiyun #define ULPI_OTG_CTRL 0x0a 22*4882a593Smuzhiyun #define ULPI_USB_INT_EN_RISE 0x0d 23*4882a593Smuzhiyun #define ULPI_USB_INT_EN_FALL 0x10 24*4882a593Smuzhiyun #define ULPI_USB_INT_STS 0x13 25*4882a593Smuzhiyun #define ULPI_USB_INT_LATCH 0x14 26*4882a593Smuzhiyun #define ULPI_DEBUG 0x15 27*4882a593Smuzhiyun #define ULPI_SCRATCH 0x16 28*4882a593Smuzhiyun /* Optional Carkit Registers */ 29*4882a593Smuzhiyun #define ULPI_CARKIT_CTRL 0x19 30*4882a593Smuzhiyun #define ULPI_CARKIT_INT_DELAY 0x1c 31*4882a593Smuzhiyun #define ULPI_CARKIT_INT_EN 0x1d 32*4882a593Smuzhiyun #define ULPI_CARKIT_INT_STS 0x20 33*4882a593Smuzhiyun #define ULPI_CARKIT_INT_LATCH 0x21 34*4882a593Smuzhiyun #define ULPI_CARKIT_PLS_CTRL 0x22 35*4882a593Smuzhiyun /* Other Optional Registers */ 36*4882a593Smuzhiyun #define ULPI_TX_POS_WIDTH 0x25 37*4882a593Smuzhiyun #define ULPI_TX_NEG_WIDTH 0x26 38*4882a593Smuzhiyun #define ULPI_POLARITY_RECOVERY 0x27 39*4882a593Smuzhiyun /* Access Extended Register Set */ 40*4882a593Smuzhiyun #define ULPI_ACCESS_EXTENDED 0x2f 41*4882a593Smuzhiyun /* Vendor Specific */ 42*4882a593Smuzhiyun #define ULPI_VENDOR_SPECIFIC 0x30 43*4882a593Smuzhiyun /* Extended Registers */ 44*4882a593Smuzhiyun #define ULPI_EXT_VENDOR_SPECIFIC 0x80 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * Register Bits 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Function Control */ 51*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_XCVRSEL BIT(0) 52*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_XCVRSEL_MASK 0x3 53*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_HIGH_SPEED 0x0 54*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_FULL_SPEED 0x1 55*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_LOW_SPEED 0x2 56*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_FS4LS 0x3 57*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_TERMSELECT BIT(2) 58*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_OPMODE BIT(3) 59*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_OPMODE_MASK (0x3 << 3) 60*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_OPMODE_NORMAL (0x0 << 3) 61*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_OPMODE_NONDRIVING (0x1 << 3) 62*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_OPMODE_DISABLE_NRZI (0x2 << 3) 63*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_OPMODE_NOSYNC_NOEOP (0x3 << 3) 64*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_RESET BIT(5) 65*4882a593Smuzhiyun #define ULPI_FUNC_CTRL_SUSPENDM BIT(6) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Interface Control */ 68*4882a593Smuzhiyun #define ULPI_IFC_CTRL_6_PIN_SERIAL_MODE BIT(0) 69*4882a593Smuzhiyun #define ULPI_IFC_CTRL_3_PIN_SERIAL_MODE BIT(1) 70*4882a593Smuzhiyun #define ULPI_IFC_CTRL_CARKITMODE BIT(2) 71*4882a593Smuzhiyun #define ULPI_IFC_CTRL_CLOCKSUSPENDM BIT(3) 72*4882a593Smuzhiyun #define ULPI_IFC_CTRL_AUTORESUME BIT(4) 73*4882a593Smuzhiyun #define ULPI_IFC_CTRL_EXTERNAL_VBUS BIT(5) 74*4882a593Smuzhiyun #define ULPI_IFC_CTRL_PASSTHRU BIT(6) 75*4882a593Smuzhiyun #define ULPI_IFC_CTRL_PROTECT_IFC_DISABLE BIT(7) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* OTG Control */ 78*4882a593Smuzhiyun #define ULPI_OTG_CTRL_ID_PULLUP BIT(0) 79*4882a593Smuzhiyun #define ULPI_OTG_CTRL_DP_PULLDOWN BIT(1) 80*4882a593Smuzhiyun #define ULPI_OTG_CTRL_DM_PULLDOWN BIT(2) 81*4882a593Smuzhiyun #define ULPI_OTG_CTRL_DISCHRGVBUS BIT(3) 82*4882a593Smuzhiyun #define ULPI_OTG_CTRL_CHRGVBUS BIT(4) 83*4882a593Smuzhiyun #define ULPI_OTG_CTRL_DRVVBUS BIT(5) 84*4882a593Smuzhiyun #define ULPI_OTG_CTRL_DRVVBUS_EXT BIT(6) 85*4882a593Smuzhiyun #define ULPI_OTG_CTRL_EXTVBUSIND BIT(7) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* USB Interrupt Enable Rising, 88*4882a593Smuzhiyun * USB Interrupt Enable Falling, 89*4882a593Smuzhiyun * USB Interrupt Status and 90*4882a593Smuzhiyun * USB Interrupt Latch 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define ULPI_INT_HOST_DISCONNECT BIT(0) 93*4882a593Smuzhiyun #define ULPI_INT_VBUS_VALID BIT(1) 94*4882a593Smuzhiyun #define ULPI_INT_SESS_VALID BIT(2) 95*4882a593Smuzhiyun #define ULPI_INT_SESS_END BIT(3) 96*4882a593Smuzhiyun #define ULPI_INT_IDGRD BIT(4) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Debug */ 99*4882a593Smuzhiyun #define ULPI_DEBUG_LINESTATE0 BIT(0) 100*4882a593Smuzhiyun #define ULPI_DEBUG_LINESTATE1 BIT(1) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Carkit Control */ 103*4882a593Smuzhiyun #define ULPI_CARKIT_CTRL_CARKITPWR BIT(0) 104*4882a593Smuzhiyun #define ULPI_CARKIT_CTRL_IDGNDDRV BIT(1) 105*4882a593Smuzhiyun #define ULPI_CARKIT_CTRL_TXDEN BIT(2) 106*4882a593Smuzhiyun #define ULPI_CARKIT_CTRL_RXDEN BIT(3) 107*4882a593Smuzhiyun #define ULPI_CARKIT_CTRL_SPKLEFTEN BIT(4) 108*4882a593Smuzhiyun #define ULPI_CARKIT_CTRL_SPKRIGHTEN BIT(5) 109*4882a593Smuzhiyun #define ULPI_CARKIT_CTRL_MICEN BIT(6) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* Carkit Interrupt Enable */ 112*4882a593Smuzhiyun #define ULPI_CARKIT_INT_EN_IDFLOAT_RISE BIT(0) 113*4882a593Smuzhiyun #define ULPI_CARKIT_INT_EN_IDFLOAT_FALL BIT(1) 114*4882a593Smuzhiyun #define ULPI_CARKIT_INT_EN_CARINTDET BIT(2) 115*4882a593Smuzhiyun #define ULPI_CARKIT_INT_EN_DP_RISE BIT(3) 116*4882a593Smuzhiyun #define ULPI_CARKIT_INT_EN_DP_FALL BIT(4) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Carkit Interrupt Status and 119*4882a593Smuzhiyun * Carkit Interrupt Latch 120*4882a593Smuzhiyun */ 121*4882a593Smuzhiyun #define ULPI_CARKIT_INT_IDFLOAT BIT(0) 122*4882a593Smuzhiyun #define ULPI_CARKIT_INT_CARINTDET BIT(1) 123*4882a593Smuzhiyun #define ULPI_CARKIT_INT_DP BIT(2) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* Carkit Pulse Control*/ 126*4882a593Smuzhiyun #define ULPI_CARKIT_PLS_CTRL_TXPLSEN BIT(0) 127*4882a593Smuzhiyun #define ULPI_CARKIT_PLS_CTRL_RXPLSEN BIT(1) 128*4882a593Smuzhiyun #define ULPI_CARKIT_PLS_CTRL_SPKRLEFT_BIASEN BIT(2) 129*4882a593Smuzhiyun #define ULPI_CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN BIT(3) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif /* __LINUX_ULPI_REGS_H */ 132