1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * TI AM33XX EMIF Routines
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2016-2017 Texas Instruments Inc.
5*4882a593Smuzhiyun * Dave Gerlach
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
8*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
9*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
13*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14*4882a593Smuzhiyun * GNU General Public License for more details.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun #ifndef __LINUX_TI_EMIF_H
17*4882a593Smuzhiyun #define __LINUX_TI_EMIF_H
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/kbuild.h>
20*4882a593Smuzhiyun #include <linux/types.h>
21*4882a593Smuzhiyun #ifndef __ASSEMBLY__
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct emif_regs_amx3 {
24*4882a593Smuzhiyun u32 emif_sdcfg_val;
25*4882a593Smuzhiyun u32 emif_timing1_val;
26*4882a593Smuzhiyun u32 emif_timing2_val;
27*4882a593Smuzhiyun u32 emif_timing3_val;
28*4882a593Smuzhiyun u32 emif_ref_ctrl_val;
29*4882a593Smuzhiyun u32 emif_zqcfg_val;
30*4882a593Smuzhiyun u32 emif_pmcr_val;
31*4882a593Smuzhiyun u32 emif_pmcr_shdw_val;
32*4882a593Smuzhiyun u32 emif_rd_wr_level_ramp_ctrl;
33*4882a593Smuzhiyun u32 emif_rd_wr_exec_thresh;
34*4882a593Smuzhiyun u32 emif_cos_config;
35*4882a593Smuzhiyun u32 emif_priority_to_cos_mapping;
36*4882a593Smuzhiyun u32 emif_connect_id_serv_1_map;
37*4882a593Smuzhiyun u32 emif_connect_id_serv_2_map;
38*4882a593Smuzhiyun u32 emif_ocp_config_val;
39*4882a593Smuzhiyun u32 emif_lpddr2_nvm_tim;
40*4882a593Smuzhiyun u32 emif_lpddr2_nvm_tim_shdw;
41*4882a593Smuzhiyun u32 emif_dll_calib_ctrl_val;
42*4882a593Smuzhiyun u32 emif_dll_calib_ctrl_val_shdw;
43*4882a593Smuzhiyun u32 emif_ddr_phy_ctlr_1;
44*4882a593Smuzhiyun u32 emif_ext_phy_ctrl_vals[120];
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct ti_emif_pm_data {
48*4882a593Smuzhiyun void __iomem *ti_emif_base_addr_virt;
49*4882a593Smuzhiyun phys_addr_t ti_emif_base_addr_phys;
50*4882a593Smuzhiyun unsigned long ti_emif_sram_config;
51*4882a593Smuzhiyun struct emif_regs_amx3 *regs_virt;
52*4882a593Smuzhiyun phys_addr_t regs_phys;
53*4882a593Smuzhiyun } __packed __aligned(8);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct ti_emif_pm_functions {
56*4882a593Smuzhiyun u32 save_context;
57*4882a593Smuzhiyun u32 restore_context;
58*4882a593Smuzhiyun u32 run_hw_leveling;
59*4882a593Smuzhiyun u32 enter_sr;
60*4882a593Smuzhiyun u32 exit_sr;
61*4882a593Smuzhiyun u32 abort_sr;
62*4882a593Smuzhiyun } __packed __aligned(8);
63*4882a593Smuzhiyun
ti_emif_asm_offsets(void)64*4882a593Smuzhiyun static inline void ti_emif_asm_offsets(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun DEFINE(EMIF_SDCFG_VAL_OFFSET,
67*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_sdcfg_val));
68*4882a593Smuzhiyun DEFINE(EMIF_TIMING1_VAL_OFFSET,
69*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_timing1_val));
70*4882a593Smuzhiyun DEFINE(EMIF_TIMING2_VAL_OFFSET,
71*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_timing2_val));
72*4882a593Smuzhiyun DEFINE(EMIF_TIMING3_VAL_OFFSET,
73*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_timing3_val));
74*4882a593Smuzhiyun DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
75*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
76*4882a593Smuzhiyun DEFINE(EMIF_ZQCFG_VAL_OFFSET,
77*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_zqcfg_val));
78*4882a593Smuzhiyun DEFINE(EMIF_PMCR_VAL_OFFSET,
79*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_pmcr_val));
80*4882a593Smuzhiyun DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
81*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
82*4882a593Smuzhiyun DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
83*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
84*4882a593Smuzhiyun DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
85*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
86*4882a593Smuzhiyun DEFINE(EMIF_COS_CONFIG_OFFSET,
87*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_cos_config));
88*4882a593Smuzhiyun DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
89*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
90*4882a593Smuzhiyun DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
91*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
92*4882a593Smuzhiyun DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
93*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
94*4882a593Smuzhiyun DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
95*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_ocp_config_val));
96*4882a593Smuzhiyun DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
97*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
98*4882a593Smuzhiyun DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
99*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
100*4882a593Smuzhiyun DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
101*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
102*4882a593Smuzhiyun DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
103*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
104*4882a593Smuzhiyun DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
105*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
106*4882a593Smuzhiyun DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
107*4882a593Smuzhiyun offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
108*4882a593Smuzhiyun DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun BLANK();
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
113*4882a593Smuzhiyun offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
114*4882a593Smuzhiyun DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
115*4882a593Smuzhiyun offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
116*4882a593Smuzhiyun DEFINE(EMIF_PM_CONFIG_OFFSET,
117*4882a593Smuzhiyun offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
118*4882a593Smuzhiyun DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
119*4882a593Smuzhiyun offsetof(struct ti_emif_pm_data, regs_virt));
120*4882a593Smuzhiyun DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
121*4882a593Smuzhiyun offsetof(struct ti_emif_pm_data, regs_phys));
122*4882a593Smuzhiyun DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun BLANK();
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
127*4882a593Smuzhiyun offsetof(struct ti_emif_pm_functions, save_context));
128*4882a593Smuzhiyun DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
129*4882a593Smuzhiyun offsetof(struct ti_emif_pm_functions, restore_context));
130*4882a593Smuzhiyun DEFINE(EMIF_PM_RUN_HW_LEVELING,
131*4882a593Smuzhiyun offsetof(struct ti_emif_pm_functions, run_hw_leveling));
132*4882a593Smuzhiyun DEFINE(EMIF_PM_ENTER_SR_OFFSET,
133*4882a593Smuzhiyun offsetof(struct ti_emif_pm_functions, enter_sr));
134*4882a593Smuzhiyun DEFINE(EMIF_PM_EXIT_SR_OFFSET,
135*4882a593Smuzhiyun offsetof(struct ti_emif_pm_functions, exit_sr));
136*4882a593Smuzhiyun DEFINE(EMIF_PM_ABORT_SR_OFFSET,
137*4882a593Smuzhiyun offsetof(struct ti_emif_pm_functions, abort_sr));
138*4882a593Smuzhiyun DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun struct gen_pool;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst);
144*4882a593Smuzhiyun int ti_emif_get_mem_type(void);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun #endif
147*4882a593Smuzhiyun #endif /* __LINUX_TI_EMIF_H */
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