1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /******************************************************************************* 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun Header file for stmmac platform data 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Copyright (C) 2009 STMicroelectronics Ltd 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10*4882a593Smuzhiyun *******************************************************************************/ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __STMMAC_PLATFORM_DATA 13*4882a593Smuzhiyun #define __STMMAC_PLATFORM_DATA 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/platform_device.h> 16*4882a593Smuzhiyun #include <linux/phy.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MTL_MAX_RX_QUEUES 8 19*4882a593Smuzhiyun #define MTL_MAX_TX_QUEUES 8 20*4882a593Smuzhiyun #define STMMAC_CH_MAX 8 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define STMMAC_RX_COE_NONE 0 23*4882a593Smuzhiyun #define STMMAC_RX_COE_TYPE1 1 24*4882a593Smuzhiyun #define STMMAC_RX_COE_TYPE2 2 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Define the macros for CSR clock range parameters to be passed by 27*4882a593Smuzhiyun * platform code. 28*4882a593Smuzhiyun * This could also be configured at run time using CPU freq framework. */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* MDC Clock Selection define*/ 31*4882a593Smuzhiyun #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ 32*4882a593Smuzhiyun #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ 33*4882a593Smuzhiyun #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ 34*4882a593Smuzhiyun #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ 35*4882a593Smuzhiyun #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ 36*4882a593Smuzhiyun #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* MTL algorithms identifiers */ 39*4882a593Smuzhiyun #define MTL_TX_ALGORITHM_WRR 0x0 40*4882a593Smuzhiyun #define MTL_TX_ALGORITHM_WFQ 0x1 41*4882a593Smuzhiyun #define MTL_TX_ALGORITHM_DWRR 0x2 42*4882a593Smuzhiyun #define MTL_TX_ALGORITHM_SP 0x3 43*4882a593Smuzhiyun #define MTL_RX_ALGORITHM_SP 0x4 44*4882a593Smuzhiyun #define MTL_RX_ALGORITHM_WSP 0x5 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* RX/TX Queue Mode */ 47*4882a593Smuzhiyun #define MTL_QUEUE_AVB 0x0 48*4882a593Smuzhiyun #define MTL_QUEUE_DCB 0x1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* The MDC clock could be set higher than the IEEE 802.3 51*4882a593Smuzhiyun * specified frequency limit 0f 2.5 MHz, by programming a clock divider 52*4882a593Smuzhiyun * of value different than the above defined values. The resultant MDIO 53*4882a593Smuzhiyun * clock frequency of 12.5 MHz is applicable for the interfacing chips 54*4882a593Smuzhiyun * supporting higher MDC clocks. 55*4882a593Smuzhiyun * The MDC clock selection macros need to be defined for MDC clock rate 56*4882a593Smuzhiyun * of 12.5 MHz, corresponding to the following selection. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ 59*4882a593Smuzhiyun #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ 60*4882a593Smuzhiyun #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ 61*4882a593Smuzhiyun #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ 62*4882a593Smuzhiyun #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ 63*4882a593Smuzhiyun #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ 64*4882a593Smuzhiyun #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ 65*4882a593Smuzhiyun #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* AXI DMA Burst length supported */ 68*4882a593Smuzhiyun #define DMA_AXI_BLEN_4 (1 << 1) 69*4882a593Smuzhiyun #define DMA_AXI_BLEN_8 (1 << 2) 70*4882a593Smuzhiyun #define DMA_AXI_BLEN_16 (1 << 3) 71*4882a593Smuzhiyun #define DMA_AXI_BLEN_32 (1 << 4) 72*4882a593Smuzhiyun #define DMA_AXI_BLEN_64 (1 << 5) 73*4882a593Smuzhiyun #define DMA_AXI_BLEN_128 (1 << 6) 74*4882a593Smuzhiyun #define DMA_AXI_BLEN_256 (1 << 7) 75*4882a593Smuzhiyun #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ 76*4882a593Smuzhiyun | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ 77*4882a593Smuzhiyun | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Platfrom data for platform device structure's platform_data field */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct stmmac_mdio_bus_data { 82*4882a593Smuzhiyun unsigned int phy_mask; 83*4882a593Smuzhiyun unsigned int has_xpcs; 84*4882a593Smuzhiyun int *irqs; 85*4882a593Smuzhiyun int probed_phy_irq; 86*4882a593Smuzhiyun bool needs_reset; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct stmmac_dma_cfg { 90*4882a593Smuzhiyun int pbl; 91*4882a593Smuzhiyun int txpbl; 92*4882a593Smuzhiyun int rxpbl; 93*4882a593Smuzhiyun bool pblx8; 94*4882a593Smuzhiyun int fixed_burst; 95*4882a593Smuzhiyun int mixed_burst; 96*4882a593Smuzhiyun bool aal; 97*4882a593Smuzhiyun bool eame; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define AXI_BLEN 7 101*4882a593Smuzhiyun struct stmmac_axi { 102*4882a593Smuzhiyun bool axi_lpi_en; 103*4882a593Smuzhiyun bool axi_xit_frm; 104*4882a593Smuzhiyun u32 axi_wr_osr_lmt; 105*4882a593Smuzhiyun u32 axi_rd_osr_lmt; 106*4882a593Smuzhiyun bool axi_kbbe; 107*4882a593Smuzhiyun u32 axi_blen[AXI_BLEN]; 108*4882a593Smuzhiyun bool axi_fb; 109*4882a593Smuzhiyun bool axi_mb; 110*4882a593Smuzhiyun bool axi_rb; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define EST_GCL 1024 114*4882a593Smuzhiyun struct stmmac_est { 115*4882a593Smuzhiyun struct mutex lock; 116*4882a593Smuzhiyun int enable; 117*4882a593Smuzhiyun u32 btr_offset[2]; 118*4882a593Smuzhiyun u32 btr[2]; 119*4882a593Smuzhiyun u32 ctr[2]; 120*4882a593Smuzhiyun u32 ter; 121*4882a593Smuzhiyun u32 gcl_unaligned[EST_GCL]; 122*4882a593Smuzhiyun u32 gcl[EST_GCL]; 123*4882a593Smuzhiyun u32 gcl_size; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun struct stmmac_rxq_cfg { 127*4882a593Smuzhiyun u8 mode_to_use; 128*4882a593Smuzhiyun u32 chan; 129*4882a593Smuzhiyun u8 pkt_route; 130*4882a593Smuzhiyun bool use_prio; 131*4882a593Smuzhiyun u32 prio; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun struct stmmac_txq_cfg { 135*4882a593Smuzhiyun u32 weight; 136*4882a593Smuzhiyun u8 mode_to_use; 137*4882a593Smuzhiyun /* Credit Base Shaper parameters */ 138*4882a593Smuzhiyun u32 send_slope; 139*4882a593Smuzhiyun u32 idle_slope; 140*4882a593Smuzhiyun u32 high_credit; 141*4882a593Smuzhiyun u32 low_credit; 142*4882a593Smuzhiyun bool use_prio; 143*4882a593Smuzhiyun u32 prio; 144*4882a593Smuzhiyun int tbs_en; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun struct plat_stmmacenet_data { 148*4882a593Smuzhiyun int bus_id; 149*4882a593Smuzhiyun int phy_addr; 150*4882a593Smuzhiyun int interface; 151*4882a593Smuzhiyun phy_interface_t phy_interface; 152*4882a593Smuzhiyun struct stmmac_mdio_bus_data *mdio_bus_data; 153*4882a593Smuzhiyun struct device_node *phy_node; 154*4882a593Smuzhiyun struct device_node *phylink_node; 155*4882a593Smuzhiyun struct device_node *mdio_node; 156*4882a593Smuzhiyun struct stmmac_dma_cfg *dma_cfg; 157*4882a593Smuzhiyun struct stmmac_est *est; 158*4882a593Smuzhiyun int clk_csr; 159*4882a593Smuzhiyun int has_gmac; 160*4882a593Smuzhiyun int enh_desc; 161*4882a593Smuzhiyun int tx_coe; 162*4882a593Smuzhiyun int rx_coe; 163*4882a593Smuzhiyun int bugged_jumbo; 164*4882a593Smuzhiyun int pmt; 165*4882a593Smuzhiyun int force_sf_dma_mode; 166*4882a593Smuzhiyun int force_thresh_dma_mode; 167*4882a593Smuzhiyun int riwt_off; 168*4882a593Smuzhiyun int max_speed; 169*4882a593Smuzhiyun int maxmtu; 170*4882a593Smuzhiyun int multicast_filter_bins; 171*4882a593Smuzhiyun int unicast_filter_entries; 172*4882a593Smuzhiyun int tx_fifo_size; 173*4882a593Smuzhiyun int rx_fifo_size; 174*4882a593Smuzhiyun int dma_tx_size; 175*4882a593Smuzhiyun int dma_rx_size; 176*4882a593Smuzhiyun int flow_ctrl; 177*4882a593Smuzhiyun u32 addr64; 178*4882a593Smuzhiyun u32 rx_queues_to_use; 179*4882a593Smuzhiyun u32 tx_queues_to_use; 180*4882a593Smuzhiyun u8 rx_sched_algorithm; 181*4882a593Smuzhiyun u8 tx_sched_algorithm; 182*4882a593Smuzhiyun struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; 183*4882a593Smuzhiyun struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; 184*4882a593Smuzhiyun void (*fix_mac_speed)(void *priv, unsigned int speed); 185*4882a593Smuzhiyun int (*serdes_powerup)(struct net_device *ndev, void *priv); 186*4882a593Smuzhiyun void (*serdes_powerdown)(struct net_device *ndev, void *priv); 187*4882a593Smuzhiyun int (*integrated_phy_power)(void *priv, bool up); 188*4882a593Smuzhiyun int (*init)(struct platform_device *pdev, void *priv); 189*4882a593Smuzhiyun void (*exit)(struct platform_device *pdev, void *priv); 190*4882a593Smuzhiyun void (*get_eth_addr)(void *priv, unsigned char *addr); 191*4882a593Smuzhiyun struct mac_device_info *(*setup)(void *priv); 192*4882a593Smuzhiyun void *bsp_priv; 193*4882a593Smuzhiyun struct clk *stmmac_clk; 194*4882a593Smuzhiyun struct clk *pclk; 195*4882a593Smuzhiyun struct clk *clk_ptp_ref; 196*4882a593Smuzhiyun unsigned int clk_ptp_rate; 197*4882a593Smuzhiyun unsigned int clk_ref_rate; 198*4882a593Smuzhiyun s32 ptp_max_adj; 199*4882a593Smuzhiyun struct reset_control *stmmac_rst; 200*4882a593Smuzhiyun struct stmmac_axi *axi; 201*4882a593Smuzhiyun int has_gmac4; 202*4882a593Smuzhiyun bool has_sun8i; 203*4882a593Smuzhiyun bool tso_en; 204*4882a593Smuzhiyun int rss_en; 205*4882a593Smuzhiyun int mac_port_sel_speed; 206*4882a593Smuzhiyun bool en_tx_lpi_clockgating; 207*4882a593Smuzhiyun int has_xgmac; 208*4882a593Smuzhiyun bool vlan_fail_q_en; 209*4882a593Smuzhiyun u8 vlan_fail_q; 210*4882a593Smuzhiyun unsigned int eee_usecs_rate; 211*4882a593Smuzhiyun bool sph_disable; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun #endif 214