1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __SPI_SH_MSIOF_H__ 3*4882a593Smuzhiyun #define __SPI_SH_MSIOF_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun enum { 6*4882a593Smuzhiyun MSIOF_SPI_MASTER, 7*4882a593Smuzhiyun MSIOF_SPI_SLAVE, 8*4882a593Smuzhiyun }; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct sh_msiof_spi_info { 11*4882a593Smuzhiyun int tx_fifo_override; 12*4882a593Smuzhiyun int rx_fifo_override; 13*4882a593Smuzhiyun u16 num_chipselect; 14*4882a593Smuzhiyun int mode; 15*4882a593Smuzhiyun unsigned int dma_tx_id; 16*4882a593Smuzhiyun unsigned int dma_rx_id; 17*4882a593Smuzhiyun u32 dtdl; 18*4882a593Smuzhiyun u32 syncdl; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #endif /* __SPI_SH_MSIOF_H__ */ 22