1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __LINUX_SPI_EEPROM_H 3*4882a593Smuzhiyun #define __LINUX_SPI_EEPROM_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/memory.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * Put one of these structures in platform_data for SPI EEPROMS handled 9*4882a593Smuzhiyun * by the "at25" driver. On SPI, most EEPROMS understand the same core 10*4882a593Smuzhiyun * command set. If you need to support EEPROMs that don't yet fit, add 11*4882a593Smuzhiyun * flags to support those protocol options. These values all come from 12*4882a593Smuzhiyun * the chip datasheets. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun struct spi_eeprom { 15*4882a593Smuzhiyun u32 byte_len; 16*4882a593Smuzhiyun char name[10]; 17*4882a593Smuzhiyun u32 page_size; /* for writes */ 18*4882a593Smuzhiyun u16 flags; 19*4882a593Smuzhiyun #define EE_ADDR1 0x0001 /* 8 bit addrs */ 20*4882a593Smuzhiyun #define EE_ADDR2 0x0002 /* 16 bit addrs */ 21*4882a593Smuzhiyun #define EE_ADDR3 0x0004 /* 24 bit addrs */ 22*4882a593Smuzhiyun #define EE_READONLY 0x0008 /* disallow writes */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * Certain EEPROMS have a size that is larger than the number of address 26*4882a593Smuzhiyun * bytes would allow (e.g. like M95040 from ST that has 512 Byte size 27*4882a593Smuzhiyun * but uses only one address byte (A0 to A7) for addressing.) For 28*4882a593Smuzhiyun * the extra address bit (A8, A16 or A24) bit 3 of the instruction byte 29*4882a593Smuzhiyun * is used. This instruction bit is normally defined as don't care for 30*4882a593Smuzhiyun * other AT25 like chips. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #define EE_INSTR_BIT3_IS_ADDR 0x0010 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun void *context; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif /* __LINUX_SPI_EEPROM_H */ 38