xref: /OK3568_Linux_fs/kernel/include/linux/soc/ti/knav_dma.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2014 Texas Instruments Incorporated
3*4882a593Smuzhiyun  * Authors:	Sandeep Nair <sandeep_n@ti.com
4*4882a593Smuzhiyun  *		Cyril Chemparathy <cyril@ti.com
5*4882a593Smuzhiyun 		Santosh Shilimkar <santosh.shilimkar@ti.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
8*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License as
9*4882a593Smuzhiyun  * published by the Free Software Foundation version 2.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12*4882a593Smuzhiyun  * kind, whether express or implied; without even the implied warranty
13*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14*4882a593Smuzhiyun  * GNU General Public License for more details.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #ifndef __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__
18*4882a593Smuzhiyun #define __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/dmaengine.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun  * PKTDMA descriptor manipulation macros for host packet descriptor
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun #define MASK(x)					(BIT(x) - 1)
26*4882a593Smuzhiyun #define KNAV_DMA_DESC_PKT_LEN_MASK		MASK(22)
27*4882a593Smuzhiyun #define KNAV_DMA_DESC_PKT_LEN_SHIFT		0
28*4882a593Smuzhiyun #define KNAV_DMA_DESC_PS_INFO_IN_SOP		BIT(22)
29*4882a593Smuzhiyun #define KNAV_DMA_DESC_PS_INFO_IN_DESC		0
30*4882a593Smuzhiyun #define KNAV_DMA_DESC_TAG_MASK			MASK(8)
31*4882a593Smuzhiyun #define KNAV_DMA_DESC_SAG_HI_SHIFT		24
32*4882a593Smuzhiyun #define KNAV_DMA_DESC_STAG_LO_SHIFT		16
33*4882a593Smuzhiyun #define KNAV_DMA_DESC_DTAG_HI_SHIFT		8
34*4882a593Smuzhiyun #define KNAV_DMA_DESC_DTAG_LO_SHIFT		0
35*4882a593Smuzhiyun #define KNAV_DMA_DESC_HAS_EPIB			BIT(31)
36*4882a593Smuzhiyun #define KNAV_DMA_DESC_NO_EPIB			0
37*4882a593Smuzhiyun #define KNAV_DMA_DESC_PSLEN_SHIFT		24
38*4882a593Smuzhiyun #define KNAV_DMA_DESC_PSLEN_MASK		MASK(6)
39*4882a593Smuzhiyun #define KNAV_DMA_DESC_ERR_FLAG_SHIFT		20
40*4882a593Smuzhiyun #define KNAV_DMA_DESC_ERR_FLAG_MASK		MASK(4)
41*4882a593Smuzhiyun #define KNAV_DMA_DESC_PSFLAG_SHIFT		16
42*4882a593Smuzhiyun #define KNAV_DMA_DESC_PSFLAG_MASK		MASK(4)
43*4882a593Smuzhiyun #define KNAV_DMA_DESC_RETQ_SHIFT		0
44*4882a593Smuzhiyun #define KNAV_DMA_DESC_RETQ_MASK			MASK(14)
45*4882a593Smuzhiyun #define KNAV_DMA_DESC_BUF_LEN_MASK		MASK(22)
46*4882a593Smuzhiyun #define KNAV_DMA_DESC_EFLAGS_MASK		MASK(4)
47*4882a593Smuzhiyun #define KNAV_DMA_DESC_EFLAGS_SHIFT		20
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define KNAV_DMA_NUM_EPIB_WORDS			4
50*4882a593Smuzhiyun #define KNAV_DMA_NUM_PS_WORDS			16
51*4882a593Smuzhiyun #define KNAV_DMA_NUM_SW_DATA_WORDS		4
52*4882a593Smuzhiyun #define KNAV_DMA_FDQ_PER_CHAN			4
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* Tx channel scheduling priority */
55*4882a593Smuzhiyun enum knav_dma_tx_priority {
56*4882a593Smuzhiyun 	DMA_PRIO_HIGH	= 0,
57*4882a593Smuzhiyun 	DMA_PRIO_MED_H,
58*4882a593Smuzhiyun 	DMA_PRIO_MED_L,
59*4882a593Smuzhiyun 	DMA_PRIO_LOW
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* Rx channel error handling mode during buffer starvation */
63*4882a593Smuzhiyun enum knav_dma_rx_err_mode {
64*4882a593Smuzhiyun 	DMA_DROP = 0,
65*4882a593Smuzhiyun 	DMA_RETRY
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* Rx flow size threshold configuration */
69*4882a593Smuzhiyun enum knav_dma_rx_thresholds {
70*4882a593Smuzhiyun 	DMA_THRESH_NONE		= 0,
71*4882a593Smuzhiyun 	DMA_THRESH_0		= 1,
72*4882a593Smuzhiyun 	DMA_THRESH_0_1		= 3,
73*4882a593Smuzhiyun 	DMA_THRESH_0_1_2	= 7
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Descriptor type */
77*4882a593Smuzhiyun enum knav_dma_desc_type {
78*4882a593Smuzhiyun 	DMA_DESC_HOST = 0,
79*4882a593Smuzhiyun 	DMA_DESC_MONOLITHIC = 2
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /**
83*4882a593Smuzhiyun  * struct knav_dma_tx_cfg:	Tx channel configuration
84*4882a593Smuzhiyun  * @filt_einfo:			Filter extended packet info
85*4882a593Smuzhiyun  * @filt_pswords:		Filter PS words present
86*4882a593Smuzhiyun  * @knav_dma_tx_priority:	Tx channel scheduling priority
87*4882a593Smuzhiyun  */
88*4882a593Smuzhiyun struct knav_dma_tx_cfg {
89*4882a593Smuzhiyun 	bool				filt_einfo;
90*4882a593Smuzhiyun 	bool				filt_pswords;
91*4882a593Smuzhiyun 	enum knav_dma_tx_priority	priority;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /**
95*4882a593Smuzhiyun  * struct knav_dma_rx_cfg:	Rx flow configuration
96*4882a593Smuzhiyun  * @einfo_present:		Extended packet info present
97*4882a593Smuzhiyun  * @psinfo_present:		PS words present
98*4882a593Smuzhiyun  * @knav_dma_rx_err_mode:	Error during buffer starvation
99*4882a593Smuzhiyun  * @knav_dma_desc_type:	Host or Monolithic desc
100*4882a593Smuzhiyun  * @psinfo_at_sop:		PS word located at start of packet
101*4882a593Smuzhiyun  * @sop_offset:			Start of packet offset
102*4882a593Smuzhiyun  * @dst_q:			Destination queue for a given flow
103*4882a593Smuzhiyun  * @thresh:			Rx flow size threshold
104*4882a593Smuzhiyun  * @fdq[]:			Free desc Queue array
105*4882a593Smuzhiyun  * @sz_thresh0:			RX packet size threshold 0
106*4882a593Smuzhiyun  * @sz_thresh1:			RX packet size threshold 1
107*4882a593Smuzhiyun  * @sz_thresh2:			RX packet size threshold 2
108*4882a593Smuzhiyun  */
109*4882a593Smuzhiyun struct knav_dma_rx_cfg {
110*4882a593Smuzhiyun 	bool				einfo_present;
111*4882a593Smuzhiyun 	bool				psinfo_present;
112*4882a593Smuzhiyun 	enum knav_dma_rx_err_mode	err_mode;
113*4882a593Smuzhiyun 	enum knav_dma_desc_type		desc_type;
114*4882a593Smuzhiyun 	bool				psinfo_at_sop;
115*4882a593Smuzhiyun 	unsigned int			sop_offset;
116*4882a593Smuzhiyun 	unsigned int			dst_q;
117*4882a593Smuzhiyun 	enum knav_dma_rx_thresholds	thresh;
118*4882a593Smuzhiyun 	unsigned int			fdq[KNAV_DMA_FDQ_PER_CHAN];
119*4882a593Smuzhiyun 	unsigned int			sz_thresh0;
120*4882a593Smuzhiyun 	unsigned int			sz_thresh1;
121*4882a593Smuzhiyun 	unsigned int			sz_thresh2;
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun /**
125*4882a593Smuzhiyun  * struct knav_dma_cfg:	Pktdma channel configuration
126*4882a593Smuzhiyun  * @sl_cfg:			Slave configuration
127*4882a593Smuzhiyun  * @tx:				Tx channel configuration
128*4882a593Smuzhiyun  * @rx:				Rx flow configuration
129*4882a593Smuzhiyun  */
130*4882a593Smuzhiyun struct knav_dma_cfg {
131*4882a593Smuzhiyun 	enum dma_transfer_direction direction;
132*4882a593Smuzhiyun 	union {
133*4882a593Smuzhiyun 		struct knav_dma_tx_cfg	tx;
134*4882a593Smuzhiyun 		struct knav_dma_rx_cfg	rx;
135*4882a593Smuzhiyun 	} u;
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /**
139*4882a593Smuzhiyun  * struct knav_dma_desc:	Host packet descriptor layout
140*4882a593Smuzhiyun  * @desc_info:			Descriptor information like id, type, length
141*4882a593Smuzhiyun  * @tag_info:			Flow tag info written in during RX
142*4882a593Smuzhiyun  * @packet_info:		Queue Manager, policy, flags etc
143*4882a593Smuzhiyun  * @buff_len:			Buffer length in bytes
144*4882a593Smuzhiyun  * @buff:			Buffer pointer
145*4882a593Smuzhiyun  * @next_desc:			For chaining the descriptors
146*4882a593Smuzhiyun  * @orig_len:			length since 'buff_len' can be overwritten
147*4882a593Smuzhiyun  * @orig_buff:			buff pointer since 'buff' can be overwritten
148*4882a593Smuzhiyun  * @epib:			Extended packet info block
149*4882a593Smuzhiyun  * @psdata:			Protocol specific
150*4882a593Smuzhiyun  * @sw_data:			Software private data not touched by h/w
151*4882a593Smuzhiyun  */
152*4882a593Smuzhiyun struct knav_dma_desc {
153*4882a593Smuzhiyun 	__le32	desc_info;
154*4882a593Smuzhiyun 	__le32	tag_info;
155*4882a593Smuzhiyun 	__le32	packet_info;
156*4882a593Smuzhiyun 	__le32	buff_len;
157*4882a593Smuzhiyun 	__le32	buff;
158*4882a593Smuzhiyun 	__le32	next_desc;
159*4882a593Smuzhiyun 	__le32	orig_len;
160*4882a593Smuzhiyun 	__le32	orig_buff;
161*4882a593Smuzhiyun 	__le32	epib[KNAV_DMA_NUM_EPIB_WORDS];
162*4882a593Smuzhiyun 	__le32	psdata[KNAV_DMA_NUM_PS_WORDS];
163*4882a593Smuzhiyun 	u32	sw_data[KNAV_DMA_NUM_SW_DATA_WORDS];
164*4882a593Smuzhiyun } ____cacheline_aligned;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_KEYSTONE_NAVIGATOR_DMA)
167*4882a593Smuzhiyun void *knav_dma_open_channel(struct device *dev, const char *name,
168*4882a593Smuzhiyun 				struct knav_dma_cfg *config);
169*4882a593Smuzhiyun void knav_dma_close_channel(void *channel);
170*4882a593Smuzhiyun int knav_dma_get_flow(void *channel);
171*4882a593Smuzhiyun bool knav_dma_device_ready(void);
172*4882a593Smuzhiyun #else
knav_dma_open_channel(struct device * dev,const char * name,struct knav_dma_cfg * config)173*4882a593Smuzhiyun static inline void *knav_dma_open_channel(struct device *dev, const char *name,
174*4882a593Smuzhiyun 				struct knav_dma_cfg *config)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	return (void *) NULL;
177*4882a593Smuzhiyun }
knav_dma_close_channel(void * channel)178*4882a593Smuzhiyun static inline void knav_dma_close_channel(void *channel)
179*4882a593Smuzhiyun {}
180*4882a593Smuzhiyun 
knav_dma_get_flow(void * channel)181*4882a593Smuzhiyun static inline int knav_dma_get_flow(void *channel)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	return -EINVAL;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
knav_dma_device_ready(void)186*4882a593Smuzhiyun static inline bool knav_dma_device_ready(void)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	return false;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun #endif
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun #endif /* __SOC_TI_KEYSTONE_NAVIGATOR_DMA_H__ */
194