1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * http://www.samsung.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Exynos - CHIPID support 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __LINUX_SOC_EXYNOS_CHIPID_H 9*4882a593Smuzhiyun #define __LINUX_SOC_EXYNOS_CHIPID_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define EXYNOS_CHIPID_REG_PRO_ID 0x00 12*4882a593Smuzhiyun #define EXYNOS_SUBREV_MASK (0xf << 4) 13*4882a593Smuzhiyun #define EXYNOS_MAINREV_MASK (0xf << 0) 14*4882a593Smuzhiyun #define EXYNOS_REV_MASK (EXYNOS_SUBREV_MASK | \ 15*4882a593Smuzhiyun EXYNOS_MAINREV_MASK) 16*4882a593Smuzhiyun #define EXYNOS_MASK 0xfffff000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define EXYNOS_CHIPID_REG_PKG_ID 0x04 19*4882a593Smuzhiyun /* Bit field definitions for EXYNOS_CHIPID_REG_PKG_ID register */ 20*4882a593Smuzhiyun #define EXYNOS5422_IDS_OFFSET 24 21*4882a593Smuzhiyun #define EXYNOS5422_IDS_MASK 0xff 22*4882a593Smuzhiyun #define EXYNOS5422_USESG_OFFSET 3 23*4882a593Smuzhiyun #define EXYNOS5422_USESG_MASK 0x01 24*4882a593Smuzhiyun #define EXYNOS5422_SG_OFFSET 0 25*4882a593Smuzhiyun #define EXYNOS5422_SG_MASK 0x07 26*4882a593Smuzhiyun #define EXYNOS5422_TABLE_OFFSET 8 27*4882a593Smuzhiyun #define EXYNOS5422_TABLE_MASK 0x03 28*4882a593Smuzhiyun #define EXYNOS5422_SG_A_OFFSET 17 29*4882a593Smuzhiyun #define EXYNOS5422_SG_A_MASK 0x0f 30*4882a593Smuzhiyun #define EXYNOS5422_SG_B_OFFSET 21 31*4882a593Smuzhiyun #define EXYNOS5422_SG_B_MASK 0x03 32*4882a593Smuzhiyun #define EXYNOS5422_SG_BSIGN_OFFSET 23 33*4882a593Smuzhiyun #define EXYNOS5422_SG_BSIGN_MASK 0x01 34*4882a593Smuzhiyun #define EXYNOS5422_BIN2_OFFSET 12 35*4882a593Smuzhiyun #define EXYNOS5422_BIN2_MASK 0x01 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define EXYNOS_CHIPID_REG_LOT_ID 0x14 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define EXYNOS_CHIPID_REG_AUX_INFO 0x1c 40*4882a593Smuzhiyun /* Bit field definitions for EXYNOS_CHIPID_REG_AUX_INFO register */ 41*4882a593Smuzhiyun #define EXYNOS5422_TMCB_OFFSET 0 42*4882a593Smuzhiyun #define EXYNOS5422_TMCB_MASK 0x7f 43*4882a593Smuzhiyun #define EXYNOS5422_ARM_UP_OFFSET 8 44*4882a593Smuzhiyun #define EXYNOS5422_ARM_UP_MASK 0x03 45*4882a593Smuzhiyun #define EXYNOS5422_ARM_DN_OFFSET 10 46*4882a593Smuzhiyun #define EXYNOS5422_ARM_DN_MASK 0x03 47*4882a593Smuzhiyun #define EXYNOS5422_KFC_UP_OFFSET 12 48*4882a593Smuzhiyun #define EXYNOS5422_KFC_UP_MASK 0x03 49*4882a593Smuzhiyun #define EXYNOS5422_KFC_DN_OFFSET 14 50*4882a593Smuzhiyun #define EXYNOS5422_KFC_DN_MASK 0x03 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif /*__LINUX_SOC_EXYNOS_CHIPID_H */ 53