1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Author: Kevin Wells <kevin.wells@nxp.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 NXP Semiconductors 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __SOC_LPC32XX_MISC_H 9*4882a593Smuzhiyun #define __SOC_LPC32XX_MISC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/types.h> 12*4882a593Smuzhiyun #include <linux/phy.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifdef CONFIG_ARCH_LPC32XX 15*4882a593Smuzhiyun extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr); 16*4882a593Smuzhiyun extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode); 17*4882a593Smuzhiyun extern void lpc32xx_loopback_set(resource_size_t mapbase, int state); 18*4882a593Smuzhiyun #else lpc32xx_return_iram(void __iomem ** mapbase,dma_addr_t * dmaaddr)19*4882a593Smuzhiyunstatic inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun *mapbase = NULL; 22*4882a593Smuzhiyun *dmaaddr = 0; 23*4882a593Smuzhiyun return 0; 24*4882a593Smuzhiyun } lpc32xx_set_phy_interface_mode(phy_interface_t mode)25*4882a593Smuzhiyunstatic inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun } lpc32xx_loopback_set(resource_size_t mapbase,int state)28*4882a593Smuzhiyunstatic inline void lpc32xx_loopback_set(resource_size_t mapbase, int state) 29*4882a593Smuzhiyun { 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __SOC_LPC32XX_MISC_H */ 34