1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __LINUX_SERIAL_SCI_H 3*4882a593Smuzhiyun #define __LINUX_SERIAL_SCI_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/bitops.h> 6*4882a593Smuzhiyun #include <linux/serial_core.h> 7*4882a593Smuzhiyun #include <linux/sh_dma.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts) 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Serial Control Register (@ = not supported by all parts) */ 14*4882a593Smuzhiyun #define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */ 15*4882a593Smuzhiyun #define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */ 16*4882a593Smuzhiyun #define SCSCR_TE BIT(5) /* Transmit Enable */ 17*4882a593Smuzhiyun #define SCSCR_RE BIT(4) /* Receive Enable */ 18*4882a593Smuzhiyun #define SCSCR_REIE BIT(3) /* Receive Error Interrupt Enable @ */ 19*4882a593Smuzhiyun #define SCSCR_TOIE BIT(2) /* Timeout Interrupt Enable @ */ 20*4882a593Smuzhiyun #define SCSCR_CKE1 BIT(1) /* Clock Enable 1 */ 21*4882a593Smuzhiyun #define SCSCR_CKE0 BIT(0) /* Clock Enable 0 */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun enum { 25*4882a593Smuzhiyun SCIx_PROBE_REGTYPE, 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun SCIx_SCI_REGTYPE, 28*4882a593Smuzhiyun SCIx_IRDA_REGTYPE, 29*4882a593Smuzhiyun SCIx_SCIFA_REGTYPE, 30*4882a593Smuzhiyun SCIx_SCIFB_REGTYPE, 31*4882a593Smuzhiyun SCIx_SH2_SCIF_FIFODATA_REGTYPE, 32*4882a593Smuzhiyun SCIx_SH3_SCIF_REGTYPE, 33*4882a593Smuzhiyun SCIx_SH4_SCIF_REGTYPE, 34*4882a593Smuzhiyun SCIx_SH4_SCIF_BRG_REGTYPE, 35*4882a593Smuzhiyun SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 36*4882a593Smuzhiyun SCIx_SH4_SCIF_FIFODATA_REGTYPE, 37*4882a593Smuzhiyun SCIx_SH7705_SCIF_REGTYPE, 38*4882a593Smuzhiyun SCIx_HSCIF_REGTYPE, 39*4882a593Smuzhiyun SCIx_RZ_SCIFA_REGTYPE, 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun SCIx_NR_REGTYPES, 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct plat_sci_port_ops { 45*4882a593Smuzhiyun void (*init_pins)(struct uart_port *, unsigned int cflag); 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Platform device specific platform_data struct 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun struct plat_sci_port { 52*4882a593Smuzhiyun unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ 53*4882a593Smuzhiyun upf_t flags; /* UPF_* flags */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun unsigned int sampling_rate; 56*4882a593Smuzhiyun unsigned int scscr; /* SCSCR initialization */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Platform overrides if necessary, defaults otherwise. 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun unsigned char regtype; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct plat_sci_port_ops *ops; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* __LINUX_SERIAL_SCI_H */ 67