1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Embedded Alley Solutions, source@embeddedalley.com. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _LINUX_SERIAL_PNX8XXX_H 7*4882a593Smuzhiyun #define _LINUX_SERIAL_PNX8XXX_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/serial_core.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PNX8XXX_NR_PORTS 2 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct pnx8xxx_port { 14*4882a593Smuzhiyun struct uart_port port; 15*4882a593Smuzhiyun struct timer_list timer; 16*4882a593Smuzhiyun unsigned int old_status; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* register offsets */ 20*4882a593Smuzhiyun #define PNX8XXX_LCR 0 21*4882a593Smuzhiyun #define PNX8XXX_MCR 0x004 22*4882a593Smuzhiyun #define PNX8XXX_BAUD 0x008 23*4882a593Smuzhiyun #define PNX8XXX_CFG 0x00c 24*4882a593Smuzhiyun #define PNX8XXX_FIFO 0x028 25*4882a593Smuzhiyun #define PNX8XXX_ISTAT 0xfe0 26*4882a593Smuzhiyun #define PNX8XXX_IEN 0xfe4 27*4882a593Smuzhiyun #define PNX8XXX_ICLR 0xfe8 28*4882a593Smuzhiyun #define PNX8XXX_ISET 0xfec 29*4882a593Smuzhiyun #define PNX8XXX_PD 0xff4 30*4882a593Smuzhiyun #define PNX8XXX_MID 0xffc 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define PNX8XXX_UART_LCR_TXBREAK (1<<30) 33*4882a593Smuzhiyun #define PNX8XXX_UART_LCR_PAREVN 0x10000000 34*4882a593Smuzhiyun #define PNX8XXX_UART_LCR_PAREN 0x08000000 35*4882a593Smuzhiyun #define PNX8XXX_UART_LCR_2STOPB 0x04000000 36*4882a593Smuzhiyun #define PNX8XXX_UART_LCR_8BIT 0x01000000 37*4882a593Smuzhiyun #define PNX8XXX_UART_LCR_TX_RST 0x00040000 38*4882a593Smuzhiyun #define PNX8XXX_UART_LCR_RX_RST 0x00020000 39*4882a593Smuzhiyun #define PNX8XXX_UART_LCR_RX_NEXT 0x00010000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define PNX8XXX_UART_MCR_SCR 0xFF000000 42*4882a593Smuzhiyun #define PNX8XXX_UART_MCR_DCD 0x00800000 43*4882a593Smuzhiyun #define PNX8XXX_UART_MCR_CTS 0x00100000 44*4882a593Smuzhiyun #define PNX8XXX_UART_MCR_LOOP 0x00000010 45*4882a593Smuzhiyun #define PNX8XXX_UART_MCR_RTS 0x00000002 46*4882a593Smuzhiyun #define PNX8XXX_UART_MCR_DTR 0x00000001 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define PNX8XXX_UART_INT_TX 0x00000080 49*4882a593Smuzhiyun #define PNX8XXX_UART_INT_EMPTY 0x00000040 50*4882a593Smuzhiyun #define PNX8XXX_UART_INT_RCVTO 0x00000020 51*4882a593Smuzhiyun #define PNX8XXX_UART_INT_RX 0x00000010 52*4882a593Smuzhiyun #define PNX8XXX_UART_INT_RXOVRN 0x00000008 53*4882a593Smuzhiyun #define PNX8XXX_UART_INT_FRERR 0x00000004 54*4882a593Smuzhiyun #define PNX8XXX_UART_INT_BREAK 0x00000002 55*4882a593Smuzhiyun #define PNX8XXX_UART_INT_PARITY 0x00000001 56*4882a593Smuzhiyun #define PNX8XXX_UART_INT_ALLRX 0x0000003F 57*4882a593Smuzhiyun #define PNX8XXX_UART_INT_ALLTX 0x000000C0 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define PNX8XXX_UART_FIFO_TXFIFO 0x001F0000 60*4882a593Smuzhiyun #define PNX8XXX_UART_FIFO_TXFIFO_STA (0x1f<<16) 61*4882a593Smuzhiyun #define PNX8XXX_UART_FIFO_RXBRK 0x00008000 62*4882a593Smuzhiyun #define PNX8XXX_UART_FIFO_RXFE 0x00004000 63*4882a593Smuzhiyun #define PNX8XXX_UART_FIFO_RXPAR 0x00002000 64*4882a593Smuzhiyun #define PNX8XXX_UART_FIFO_RXFIFO 0x00001F00 65*4882a593Smuzhiyun #define PNX8XXX_UART_FIFO_RBRTHR 0x000000FF 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif 68