1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _LINUX_SERIAL_BCM63XX_H 3*4882a593Smuzhiyun #define _LINUX_SERIAL_BCM63XX_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* UART Control Register */ 6*4882a593Smuzhiyun #define UART_CTL_REG 0x0 7*4882a593Smuzhiyun #define UART_CTL_RXTMOUTCNT_SHIFT 0 8*4882a593Smuzhiyun #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) 9*4882a593Smuzhiyun #define UART_CTL_RSTTXDN_SHIFT 5 10*4882a593Smuzhiyun #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) 11*4882a593Smuzhiyun #define UART_CTL_RSTRXFIFO_SHIFT 6 12*4882a593Smuzhiyun #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) 13*4882a593Smuzhiyun #define UART_CTL_RSTTXFIFO_SHIFT 7 14*4882a593Smuzhiyun #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) 15*4882a593Smuzhiyun #define UART_CTL_STOPBITS_SHIFT 8 16*4882a593Smuzhiyun #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) 17*4882a593Smuzhiyun #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) 18*4882a593Smuzhiyun #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) 19*4882a593Smuzhiyun #define UART_CTL_BITSPERSYM_SHIFT 12 20*4882a593Smuzhiyun #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) 21*4882a593Smuzhiyun #define UART_CTL_XMITBRK_SHIFT 14 22*4882a593Smuzhiyun #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) 23*4882a593Smuzhiyun #define UART_CTL_RSVD_SHIFT 15 24*4882a593Smuzhiyun #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) 25*4882a593Smuzhiyun #define UART_CTL_RXPAREVEN_SHIFT 16 26*4882a593Smuzhiyun #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) 27*4882a593Smuzhiyun #define UART_CTL_RXPAREN_SHIFT 17 28*4882a593Smuzhiyun #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) 29*4882a593Smuzhiyun #define UART_CTL_TXPAREVEN_SHIFT 18 30*4882a593Smuzhiyun #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) 31*4882a593Smuzhiyun #define UART_CTL_TXPAREN_SHIFT 18 32*4882a593Smuzhiyun #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) 33*4882a593Smuzhiyun #define UART_CTL_LOOPBACK_SHIFT 20 34*4882a593Smuzhiyun #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) 35*4882a593Smuzhiyun #define UART_CTL_RXEN_SHIFT 21 36*4882a593Smuzhiyun #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) 37*4882a593Smuzhiyun #define UART_CTL_TXEN_SHIFT 22 38*4882a593Smuzhiyun #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) 39*4882a593Smuzhiyun #define UART_CTL_BRGEN_SHIFT 23 40*4882a593Smuzhiyun #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* UART Baudword register */ 43*4882a593Smuzhiyun #define UART_BAUD_REG 0x4 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* UART Misc Control register */ 46*4882a593Smuzhiyun #define UART_MCTL_REG 0x8 47*4882a593Smuzhiyun #define UART_MCTL_DTR_SHIFT 0 48*4882a593Smuzhiyun #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) 49*4882a593Smuzhiyun #define UART_MCTL_RTS_SHIFT 1 50*4882a593Smuzhiyun #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) 51*4882a593Smuzhiyun #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 52*4882a593Smuzhiyun #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) 53*4882a593Smuzhiyun #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 54*4882a593Smuzhiyun #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) 55*4882a593Smuzhiyun #define UART_MCTL_RXFIFOFILL_SHIFT 16 56*4882a593Smuzhiyun #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) 57*4882a593Smuzhiyun #define UART_MCTL_TXFIFOFILL_SHIFT 24 58*4882a593Smuzhiyun #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* UART External Input Configuration register */ 61*4882a593Smuzhiyun #define UART_EXTINP_REG 0xc 62*4882a593Smuzhiyun #define UART_EXTINP_RI_SHIFT 0 63*4882a593Smuzhiyun #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) 64*4882a593Smuzhiyun #define UART_EXTINP_CTS_SHIFT 1 65*4882a593Smuzhiyun #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) 66*4882a593Smuzhiyun #define UART_EXTINP_DCD_SHIFT 2 67*4882a593Smuzhiyun #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) 68*4882a593Smuzhiyun #define UART_EXTINP_DSR_SHIFT 3 69*4882a593Smuzhiyun #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) 70*4882a593Smuzhiyun #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) 71*4882a593Smuzhiyun #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) 72*4882a593Smuzhiyun #define UART_EXTINP_IR_RI 0 73*4882a593Smuzhiyun #define UART_EXTINP_IR_CTS 1 74*4882a593Smuzhiyun #define UART_EXTINP_IR_DCD 2 75*4882a593Smuzhiyun #define UART_EXTINP_IR_DSR 3 76*4882a593Smuzhiyun #define UART_EXTINP_RI_NOSENSE_SHIFT 16 77*4882a593Smuzhiyun #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) 78*4882a593Smuzhiyun #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 79*4882a593Smuzhiyun #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) 80*4882a593Smuzhiyun #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 81*4882a593Smuzhiyun #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) 82*4882a593Smuzhiyun #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 83*4882a593Smuzhiyun #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* UART Interrupt register */ 86*4882a593Smuzhiyun #define UART_IR_REG 0x10 87*4882a593Smuzhiyun #define UART_IR_MASK(x) (1 << (x + 16)) 88*4882a593Smuzhiyun #define UART_IR_STAT(x) (1 << (x)) 89*4882a593Smuzhiyun #define UART_IR_EXTIP 0 90*4882a593Smuzhiyun #define UART_IR_TXUNDER 1 91*4882a593Smuzhiyun #define UART_IR_TXOVER 2 92*4882a593Smuzhiyun #define UART_IR_TXTRESH 3 93*4882a593Smuzhiyun #define UART_IR_TXRDLATCH 4 94*4882a593Smuzhiyun #define UART_IR_TXEMPTY 5 95*4882a593Smuzhiyun #define UART_IR_RXUNDER 6 96*4882a593Smuzhiyun #define UART_IR_RXOVER 7 97*4882a593Smuzhiyun #define UART_IR_RXTIMEOUT 8 98*4882a593Smuzhiyun #define UART_IR_RXFULL 9 99*4882a593Smuzhiyun #define UART_IR_RXTHRESH 10 100*4882a593Smuzhiyun #define UART_IR_RXNOTEMPTY 11 101*4882a593Smuzhiyun #define UART_IR_RXFRAMEERR 12 102*4882a593Smuzhiyun #define UART_IR_RXPARERR 13 103*4882a593Smuzhiyun #define UART_IR_RXBRK 14 104*4882a593Smuzhiyun #define UART_IR_TXDONE 15 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* UART Fifo register */ 107*4882a593Smuzhiyun #define UART_FIFO_REG 0x14 108*4882a593Smuzhiyun #define UART_FIFO_VALID_SHIFT 0 109*4882a593Smuzhiyun #define UART_FIFO_VALID_MASK 0xff 110*4882a593Smuzhiyun #define UART_FIFO_FRAMEERR_SHIFT 8 111*4882a593Smuzhiyun #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) 112*4882a593Smuzhiyun #define UART_FIFO_PARERR_SHIFT 9 113*4882a593Smuzhiyun #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) 114*4882a593Smuzhiyun #define UART_FIFO_BRKDET_SHIFT 10 115*4882a593Smuzhiyun #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) 116*4882a593Smuzhiyun #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ 117*4882a593Smuzhiyun UART_FIFO_PARERR_MASK | \ 118*4882a593Smuzhiyun UART_FIFO_BRKDET_MASK) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* _LINUX_SERIAL_BCM63XX_H */ 121