1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* $Id: scc.h,v 1.29 1997/04/02 14:56:45 jreuter Exp jreuter $ */ 3*4882a593Smuzhiyun #ifndef _SCC_H 4*4882a593Smuzhiyun #define _SCC_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include <uapi/linux/scc.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun enum {TX_OFF, TX_ON}; /* command for scc_key_trx() */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Vector masks in RR2B */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define VECTOR_MASK 0x06 14*4882a593Smuzhiyun #define TXINT 0x00 15*4882a593Smuzhiyun #define EXINT 0x02 16*4882a593Smuzhiyun #define RXINT 0x04 17*4882a593Smuzhiyun #define SPINT 0x06 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifdef CONFIG_SCC_DELAY 20*4882a593Smuzhiyun #define Inb(port) inb_p(port) 21*4882a593Smuzhiyun #define Outb(port, val) outb_p(val, port) 22*4882a593Smuzhiyun #else 23*4882a593Smuzhiyun #define Inb(port) inb(port) 24*4882a593Smuzhiyun #define Outb(port, val) outb(val, port) 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* SCC channel control structure for KISS */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct scc_kiss { 30*4882a593Smuzhiyun unsigned char txdelay; /* Transmit Delay 10 ms/cnt */ 31*4882a593Smuzhiyun unsigned char persist; /* Persistence (0-255) as a % */ 32*4882a593Smuzhiyun unsigned char slottime; /* Delay to wait on persistence hit */ 33*4882a593Smuzhiyun unsigned char tailtime; /* Delay after last byte written */ 34*4882a593Smuzhiyun unsigned char fulldup; /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */ 35*4882a593Smuzhiyun unsigned char waittime; /* Waittime before any transmit attempt */ 36*4882a593Smuzhiyun unsigned int maxkeyup; /* Maximum time to transmit (seconds) */ 37*4882a593Smuzhiyun unsigned int mintime; /* Minimal offtime after MAXKEYUP timeout (seconds) */ 38*4882a593Smuzhiyun unsigned int idletime; /* Maximum idle time in ALWAYS KEYED mode (seconds) */ 39*4882a593Smuzhiyun unsigned int maxdefer; /* Timer for CSMA channel busy limit */ 40*4882a593Smuzhiyun unsigned char tx_inhibit; /* Transmit is not allowed when set */ 41*4882a593Smuzhiyun unsigned char group; /* Group ID for AX.25 TX interlocking */ 42*4882a593Smuzhiyun unsigned char mode; /* 'normal' or 'hwctrl' mode (unused) */ 43*4882a593Smuzhiyun unsigned char softdcd; /* Use DPLL instead of DCD pin for carrier detect */ 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* SCC channel structure */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct scc_channel { 50*4882a593Smuzhiyun int init; /* channel exists? */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct net_device *dev; /* link to device control structure */ 53*4882a593Smuzhiyun struct net_device_stats dev_stat;/* device statistics */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun char brand; /* manufacturer of the board */ 56*4882a593Smuzhiyun long clock; /* used clock */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun io_port ctrl; /* I/O address of CONTROL register */ 59*4882a593Smuzhiyun io_port data; /* I/O address of DATA register */ 60*4882a593Smuzhiyun io_port special; /* I/O address of special function port */ 61*4882a593Smuzhiyun int irq; /* Number of Interrupt */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun char option; 64*4882a593Smuzhiyun char enhanced; /* Enhanced SCC support */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun unsigned char wreg[16]; /* Copy of last written value in WRx */ 67*4882a593Smuzhiyun unsigned char status; /* Copy of R0 at last external interrupt */ 68*4882a593Smuzhiyun unsigned char dcd; /* DCD status */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct scc_kiss kiss; /* control structure for KISS params */ 71*4882a593Smuzhiyun struct scc_stat stat; /* statistical information */ 72*4882a593Smuzhiyun struct scc_modem modem; /* modem information */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun struct sk_buff_head tx_queue; /* next tx buffer */ 75*4882a593Smuzhiyun struct sk_buff *rx_buff; /* pointer to frame currently received */ 76*4882a593Smuzhiyun struct sk_buff *tx_buff; /* pointer to frame currently transmitted */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Timer */ 79*4882a593Smuzhiyun struct timer_list tx_t; /* tx timer for this channel */ 80*4882a593Smuzhiyun struct timer_list tx_wdog; /* tx watchdogs */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Channel lock */ 83*4882a593Smuzhiyun spinlock_t lock; /* Channel guard lock */ 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* defined(_SCC_H) */ 87