1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/linux/rtc/m48t59.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Definitions for the platform data of m48t59 RTC chip driver. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (c) 2007 Wind River Systems, Inc. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Mark Zhan <rongkai.zhan@windriver.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _LINUX_RTC_M48T59_H_ 13*4882a593Smuzhiyun #define _LINUX_RTC_M48T59_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * M48T59 Register Offset 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define M48T59_YEAR 0xf 19*4882a593Smuzhiyun #define M48T59_MONTH 0xe 20*4882a593Smuzhiyun #define M48T59_MDAY 0xd /* Day of Month */ 21*4882a593Smuzhiyun #define M48T59_WDAY 0xc /* Day of Week */ 22*4882a593Smuzhiyun #define M48T59_WDAY_CB 0x20 /* Century Bit */ 23*4882a593Smuzhiyun #define M48T59_WDAY_CEB 0x10 /* Century Enable Bit */ 24*4882a593Smuzhiyun #define M48T59_HOUR 0xb 25*4882a593Smuzhiyun #define M48T59_MIN 0xa 26*4882a593Smuzhiyun #define M48T59_SEC 0x9 27*4882a593Smuzhiyun #define M48T59_CNTL 0x8 28*4882a593Smuzhiyun #define M48T59_CNTL_READ 0x40 29*4882a593Smuzhiyun #define M48T59_CNTL_WRITE 0x80 30*4882a593Smuzhiyun #define M48T59_WATCHDOG 0x7 31*4882a593Smuzhiyun #define M48T59_INTR 0x6 32*4882a593Smuzhiyun #define M48T59_INTR_AFE 0x80 /* Alarm Interrupt Enable */ 33*4882a593Smuzhiyun #define M48T59_INTR_ABE 0x20 34*4882a593Smuzhiyun #define M48T59_ALARM_DATE 0x5 35*4882a593Smuzhiyun #define M48T59_ALARM_HOUR 0x4 36*4882a593Smuzhiyun #define M48T59_ALARM_MIN 0x3 37*4882a593Smuzhiyun #define M48T59_ALARM_SEC 0x2 38*4882a593Smuzhiyun #define M48T59_UNUSED 0x1 39*4882a593Smuzhiyun #define M48T59_FLAGS 0x0 40*4882a593Smuzhiyun #define M48T59_FLAGS_WDT 0x80 /* watchdog timer expired */ 41*4882a593Smuzhiyun #define M48T59_FLAGS_AF 0x40 /* alarm */ 42*4882a593Smuzhiyun #define M48T59_FLAGS_BF 0x10 /* low battery */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define M48T59RTC_TYPE_M48T59 0 /* to keep compatibility */ 45*4882a593Smuzhiyun #define M48T59RTC_TYPE_M48T02 1 46*4882a593Smuzhiyun #define M48T59RTC_TYPE_M48T08 2 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct m48t59_plat_data { 49*4882a593Smuzhiyun /* The method to access M48T59 registers */ 50*4882a593Smuzhiyun void (*write_byte)(struct device *dev, u32 ofs, u8 val); 51*4882a593Smuzhiyun unsigned char (*read_byte)(struct device *dev, u32 ofs); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun int type; /* RTC model */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* ioaddr mapped externally */ 56*4882a593Smuzhiyun void __iomem *ioaddr; 57*4882a593Smuzhiyun /* offset to RTC registers, automatically set according to the type */ 58*4882a593Smuzhiyun unsigned int offset; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* _LINUX_RTC_M48T59_H_ */ 62