1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __ROCKCHIP_PSCI_H
3*4882a593Smuzhiyun #define __ROCKCHIP_PSCI_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #define SEC_REG_RD (0x0)
6*4882a593Smuzhiyun #define SEC_REG_WR (0x1)
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun * trust firmware verison
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
12*4882a593Smuzhiyun #define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun * pcsi smc funciton id
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun #define PSCI_SIP_RKTF_VER (0x82000001)
18*4882a593Smuzhiyun #define PSCI_SIP_ACCESS_REG (0x82000002)
19*4882a593Smuzhiyun #define PSCI_SIP_ACCESS_REG64 (0xc2000002)
20*4882a593Smuzhiyun #define PSCI_SIP_SUSPEND_WR_CTRBITS (0x82000003)
21*4882a593Smuzhiyun #define PSCI_SIP_PENDING_CPUS (0x82000004)
22*4882a593Smuzhiyun #define PSCI_SIP_UARTDBG_CFG (0x82000005)
23*4882a593Smuzhiyun #define PSCI_SIP_UARTDBG_CFG64 (0xc2000005)
24*4882a593Smuzhiyun #define PSCI_SIP_EL3FIQ_CFG (0x82000006)
25*4882a593Smuzhiyun #define PSCI_SIP_SMEM_CONFIG (0x82000007)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * pcsi smc funciton err code
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun #define PSCI_SMC_FUNC_UNK 0xffffffff
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * define PSCI_SIP_UARTDBG_CFG call type
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun #define UARTDBG_CFG_INIT 0xf0
36*4882a593Smuzhiyun #define UARTDBG_CFG_OSHDL_TO_OS 0xf1
37*4882a593Smuzhiyun #define UARTDBG_CFG_OSHDL_CPUSW 0xf3
38*4882a593Smuzhiyun #define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
39*4882a593Smuzhiyun #define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * rockchip psci function call interface
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun u32 rockchip_psci_smc_read(u32 function_id, u32 arg0, u32 arg1, u32 arg2,
46*4882a593Smuzhiyun u32 *val);
47*4882a593Smuzhiyun u32 rockchip_psci_smc_write(u32 function_id, u32 arg0, u32 arg1, u32 arg2);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun u32 rockchip_psci_smc_get_tf_ver(void);
50*4882a593Smuzhiyun u32 rockchip_secure_reg_read(u32 addr_phy);
51*4882a593Smuzhiyun u32 rockchip_secure_reg_write(u32 addr_phy, u32 val);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #ifdef CONFIG_ARM64
54*4882a593Smuzhiyun u32 rockchip_psci_smc_write64(u64 function_id, u64 arg0, u64 arg1, u64 arg2);
55*4882a593Smuzhiyun u32 rockchip_psci_smc_read64(u64 function_id, u64 arg0, u64 arg1, u64 arg2,
56*4882a593Smuzhiyun u64 *val);
57*4882a593Smuzhiyun u64 rockchip_secure_reg_read64(u64 addr_phy);
58*4882a593Smuzhiyun u32 rockchip_secure_reg_write64(u64 addr_phy, u64 val);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun void psci_fiq_debugger_uart_irq_tf_cb(u64 sp_el1, u64 offset);
61*4882a593Smuzhiyun #endif
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun u32 psci_fiq_debugger_switch_cpu(u32 cpu);
64*4882a593Smuzhiyun void psci_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback);
65*4882a593Smuzhiyun void psci_fiq_debugger_enable_debug(bool val);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #if defined(CONFIG_ARM_PSCI) || defined(CONFIG_ARM64)
68*4882a593Smuzhiyun u32 psci_set_memory_secure(bool val);
69*4882a593Smuzhiyun #else
psci_set_memory_secure(bool val)70*4882a593Smuzhiyun static inline u32 psci_set_memory_secure(bool val)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #endif /* __ROCKCHIP_PSCI_H */
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