1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __MACH_ROCKCHIP_GRF_H 3*4882a593Smuzhiyun #define __MACH_ROCKCHIP_GRF_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define RK3188_GRF_GPIO0L_DIR 0x0000 6*4882a593Smuzhiyun #define RK3188_GRF_GPIO0H_DIR 0x0004 7*4882a593Smuzhiyun #define RK3188_GRF_GPIO1L_DIR 0x0008 8*4882a593Smuzhiyun #define RK3188_GRF_GPIO1H_DIR 0x000c 9*4882a593Smuzhiyun #define RK3188_GRF_GPIO2L_DIR 0x0010 10*4882a593Smuzhiyun #define RK3188_GRF_GPIO2H_DIR 0x0014 11*4882a593Smuzhiyun #define RK3188_GRF_GPIO3L_DIR 0x0018 12*4882a593Smuzhiyun #define RK3188_GRF_GPIO3H_DIR 0x001c 13*4882a593Smuzhiyun #define RK3188_GRF_GPIO0L_DO 0x0020 14*4882a593Smuzhiyun #define RK3188_GRF_GPIO0H_DO 0x0024 15*4882a593Smuzhiyun #define RK3188_GRF_GPIO1L_DO 0x0028 16*4882a593Smuzhiyun #define RK3188_GRF_GPIO1H_DO 0x002c 17*4882a593Smuzhiyun #define RK3188_GRF_GPIO2L_DO 0x0030 18*4882a593Smuzhiyun #define RK3188_GRF_GPIO2H_DO 0x0034 19*4882a593Smuzhiyun #define RK3188_GRF_GPIO3L_DO 0x0038 20*4882a593Smuzhiyun #define RK3188_GRF_GPIO3H_DO 0x003c 21*4882a593Smuzhiyun #define RK3188_GRF_GPIO0L_EN 0x0040 22*4882a593Smuzhiyun #define RK3188_GRF_GPIO0H_EN 0x0044 23*4882a593Smuzhiyun #define RK3188_GRF_GPIO1L_EN 0x0048 24*4882a593Smuzhiyun #define RK3188_GRF_GPIO1H_EN 0x004c 25*4882a593Smuzhiyun #define RK3188_GRF_GPIO2L_EN 0x0050 26*4882a593Smuzhiyun #define RK3188_GRF_GPIO2H_EN 0x0054 27*4882a593Smuzhiyun #define RK3188_GRF_GPIO3L_EN 0x0058 28*4882a593Smuzhiyun #define RK3188_GRF_GPIO3H_EN 0x005c 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define RK3188_GRF_GPIO0C_IOMUX 0x0068 31*4882a593Smuzhiyun #define RK3188_GRF_GPIO0D_IOMUX 0x006c 32*4882a593Smuzhiyun #define RK3188_GRF_GPIO1A_IOMUX 0x0070 33*4882a593Smuzhiyun #define RK3188_GRF_GPIO1B_IOMUX 0x0074 34*4882a593Smuzhiyun #define RK3188_GRF_GPIO1C_IOMUX 0x0078 35*4882a593Smuzhiyun #define RK3188_GRF_GPIO1D_IOMUX 0x007c 36*4882a593Smuzhiyun #define RK3188_GRF_GPIO2A_IOMUX 0x0080 37*4882a593Smuzhiyun #define RK3188_GRF_GPIO2B_IOMUX 0x0084 38*4882a593Smuzhiyun #define RK3188_GRF_GPIO2C_IOMUX 0x0088 39*4882a593Smuzhiyun #define RK3188_GRF_GPIO2D_IOMUX 0x008c 40*4882a593Smuzhiyun #define RK3188_GRF_GPIO3A_IOMUX 0x0090 41*4882a593Smuzhiyun #define RK3188_GRF_GPIO3B_IOMUX 0x0094 42*4882a593Smuzhiyun #define RK3188_GRF_GPIO3C_IOMUX 0x0098 43*4882a593Smuzhiyun #define RK3188_GRF_GPIO3D_IOMUX 0x009c 44*4882a593Smuzhiyun #define RK3188_GRF_SOC_CON0 0x00a0 45*4882a593Smuzhiyun #define RK3188_GRF_SOC_CON1 0x00a4 46*4882a593Smuzhiyun #define RK3188_GRF_SOC_CON2 0x00a8 47*4882a593Smuzhiyun #define RK3188_GRF_SOC_STATUS0 0x00ac 48*4882a593Smuzhiyun #define RK3188_GRF_DMAC1_CON0 0x00b0 49*4882a593Smuzhiyun #define RK3188_GRF_DMAC1_CON1 0x00b4 50*4882a593Smuzhiyun #define RK3188_GRF_DMAC1_CON2 0x00b8 51*4882a593Smuzhiyun #define RK3188_GRF_DMAC2_CON0 0x00bc 52*4882a593Smuzhiyun #define RK3188_GRF_DMAC2_CON1 0x00c0 53*4882a593Smuzhiyun #define RK3188_GRF_DMAC2_CON2 0x00c4 54*4882a593Smuzhiyun #define RK3188_GRF_DMAC2_CON3 0x00c8 55*4882a593Smuzhiyun #define RK3188_GRF_CPU_CON0 0x00cc 56*4882a593Smuzhiyun #define RK3188_GRF_CPU_CON1 0x00d0 57*4882a593Smuzhiyun #define RK3188_GRF_CPU_CON2 0x00d4 58*4882a593Smuzhiyun #define RK3188_GRF_CPU_CON3 0x00d8 59*4882a593Smuzhiyun #define RK3188_GRF_CPU_CON4 0x00dc 60*4882a593Smuzhiyun #define RK3188_GRF_CPU_CON5 0x00e0 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define RK3188_GRF_DDRC_CON0 0x00ec 63*4882a593Smuzhiyun #define RK3188_GRF_DDRC_STAT 0x00f0 64*4882a593Smuzhiyun #define RK3188_GRF_IO_CON0 0x00f4 65*4882a593Smuzhiyun #define RK3188_GRF_IO_CON1 0x00f8 66*4882a593Smuzhiyun #define RK3188_GRF_IO_CON2 0x00fc 67*4882a593Smuzhiyun #define RK3188_GRF_IO_CON3 0x0100 68*4882a593Smuzhiyun #define RK3188_GRF_IO_CON4 0x0104 69*4882a593Smuzhiyun #define RK3188_GRF_SOC_STATUS1 0x0108 70*4882a593Smuzhiyun #define RK3188_GRF_UOC0_CON0 0x010c 71*4882a593Smuzhiyun #define RK3188_GRF_UOC0_CON1 0x0110 72*4882a593Smuzhiyun #define RK3188_GRF_UOC0_CON2 0x0114 73*4882a593Smuzhiyun #define RK3188_GRF_UOC0_CON3 0x0118 74*4882a593Smuzhiyun #define RK3188_GRF_UOC1_CON0 0x011c 75*4882a593Smuzhiyun #define RK3188_GRF_UOC1_CON1 0x0120 76*4882a593Smuzhiyun #define RK3188_GRF_UOC1_CON2 0x0124 77*4882a593Smuzhiyun #define RK3188_GRF_UOC1_CON3 0x0128 78*4882a593Smuzhiyun #define RK3188_GRF_UOC2_CON0 0x012c 79*4882a593Smuzhiyun #define RK3188_GRF_UOC2_CON1 0x0130 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define RK3188_GRF_UOC3_CON0 0x0138 82*4882a593Smuzhiyun #define RK3188_GRF_UOC3_CON1 0x013c 83*4882a593Smuzhiyun #define RK3188_GRF_EHCI_STAT 0x0140 84*4882a593Smuzhiyun #define RK3188_GRF_OS_REG0 0x0144 85*4882a593Smuzhiyun #define RK3188_GRF_OS_REG1 0x0148 86*4882a593Smuzhiyun #define RK3188_GRF_OS_REG2 0x014c 87*4882a593Smuzhiyun #define RK3188_GRF_OS_REG3 0x0150 88*4882a593Smuzhiyun #define RK3188_GRF_OS_REG4 0x0154 89*4882a593Smuzhiyun #define RK3188_GRF_OS_REG5 0x0158 90*4882a593Smuzhiyun #define RK3188_GRF_OS_REG6 0x015c 91*4882a593Smuzhiyun #define RK3188_GRF_OS_REG7 0x0160 92*4882a593Smuzhiyun #define RK3188_GRF_GPIO0B_PULL 0x0164 93*4882a593Smuzhiyun #define RK3188_GRF_GPIO0C_PULL 0x0168 94*4882a593Smuzhiyun #define RK3188_GRF_GPIO0D_PULL 0x016c 95*4882a593Smuzhiyun #define RK3188_GRF_GPIO1A_PULL 0x0170 96*4882a593Smuzhiyun #define RK3188_GRF_GPIO1B_PULL 0x0174 97*4882a593Smuzhiyun #define RK3188_GRF_GPIO1C_PULL 0x0178 98*4882a593Smuzhiyun #define RK3188_GRF_GPIO1D_PULL 0x017c 99*4882a593Smuzhiyun #define RK3188_GRF_GPIO2A_PULL 0x0180 100*4882a593Smuzhiyun #define RK3188_GRF_GPIO2B_PULL 0x0184 101*4882a593Smuzhiyun #define RK3188_GRF_GPIO2C_PULL 0x0188 102*4882a593Smuzhiyun #define RK3188_GRF_GPIO2D_PULL 0x018c 103*4882a593Smuzhiyun #define RK3188_GRF_GPIO3A_PULL 0x0190 104*4882a593Smuzhiyun #define RK3188_GRF_GPIO3B_PULL 0x0194 105*4882a593Smuzhiyun #define RK3188_GRF_GPIO3C_PULL 0x0198 106*4882a593Smuzhiyun #define RK3188_GRF_GPIO3D_PULL 0x019c 107*4882a593Smuzhiyun #define RK3188_GRF_FLASH_DATA_PULL 0x01a0 108*4882a593Smuzhiyun #define RK3188_GRF_FLASH_CMD_PULL 0x01a4 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define RK3288_GRF_GPIO0_A_IOMUX 0x0084 112*4882a593Smuzhiyun #define RK3288_GRF_GPIO0_B_IOMUX 0x0088 113*4882a593Smuzhiyun #define RK3288_GRF_GPIO0_C_IOMUX 0x008c 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define RK3288_GRF_GPIO1D_IOMUX 0x000c 116*4882a593Smuzhiyun #define RK3288_GRF_GPIO2A_IOMUX 0x0010 117*4882a593Smuzhiyun #define RK3288_GRF_GPIO2B_IOMUX 0x0014 118*4882a593Smuzhiyun #define RK3288_GRF_GPIO2C_IOMUX 0x0018 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define RK3288_GRF_GPIO3A_IOMUX 0x0020 121*4882a593Smuzhiyun #define RK3288_GRF_GPIO3B_IOMUX 0x0024 122*4882a593Smuzhiyun #define RK3288_GRF_GPIO3C_IOMUX 0x0028 123*4882a593Smuzhiyun #define RK3288_GRF_GPIO3DL_IOMUX 0x002c 124*4882a593Smuzhiyun #define RK3288_GRF_GPIO3DH_IOMUX 0x0030 125*4882a593Smuzhiyun #define RK3288_GRF_GPIO4AL_IOMUX 0x0034 126*4882a593Smuzhiyun #define RK3288_GRF_GPIO4AH_IOMUX 0x0038 127*4882a593Smuzhiyun #define RK3288_GRF_GPIO4BL_IOMUX 0x003c 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define RK3288_GRF_GPIO4C_IOMUX 0x0044 130*4882a593Smuzhiyun #define RK3288_GRF_GPIO4D_IOMUX 0x0048 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define RK3288_GRF_GPIO5B_IOMUX 0x0050 133*4882a593Smuzhiyun #define RK3288_GRF_GPIO5C_IOMUX 0x0054 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define RK3288_GRF_GPIO6A_IOMUX 0x005c 136*4882a593Smuzhiyun #define RK3288_GRF_GPIO6B_IOMUX 0x0060 137*4882a593Smuzhiyun #define RK3288_GRF_GPIO6C_IOMUX 0x0064 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define RK3288_GRF_GPIO7A_IOMUX 0x006c 140*4882a593Smuzhiyun #define RK3288_GRF_GPIO7B_IOMUX 0x0070 141*4882a593Smuzhiyun #define RK3288_GRF_GPIO7CL_IOMUX 0x0074 142*4882a593Smuzhiyun #define RK3288_GRF_GPIO7CH_IOMUX 0x0078 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define RK3288_GRF_GPIO8A_IOMUX 0x0080 145*4882a593Smuzhiyun #define RK3288_GRF_GPIO8B_IOMUX 0x0084 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define RK3288_GRF_GPIO1H_SR 0x0104 148*4882a593Smuzhiyun #define RK3288_GRF_GPIO2L_SR 0x0108 149*4882a593Smuzhiyun #define RK3288_GRF_GPIO2H_SR 0x010c 150*4882a593Smuzhiyun #define RK3288_GRF_GPIO3L_SR 0x0110 151*4882a593Smuzhiyun #define RK3288_GRF_GPIO3H_SR 0x0114 152*4882a593Smuzhiyun #define RK3288_GRF_GPIO4L_SR 0x0118 153*4882a593Smuzhiyun #define RK3288_GRF_GPIO4H_SR 0x011c 154*4882a593Smuzhiyun #define RK3288_GRF_GPIO5L_SR 0x0120 155*4882a593Smuzhiyun #define RK3288_GRF_GPIO5H_SR 0x0124 156*4882a593Smuzhiyun #define RK3288_GRF_GPIO6L_SR 0x0128 157*4882a593Smuzhiyun #define RK3288_GRF_GPIO6H_SR 0x012c 158*4882a593Smuzhiyun #define RK3288_GRF_GPIO7L_SR 0x0130 159*4882a593Smuzhiyun #define RK3288_GRF_GPIO7H_SR 0x0134 160*4882a593Smuzhiyun #define RK3288_GRF_GPIO8L_SR 0x0138 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define RK3288_GRF_GPIO1D_P 0x014c 163*4882a593Smuzhiyun #define RK3288_GRF_GPIO2A_P 0x0150 164*4882a593Smuzhiyun #define RK3288_GRF_GPIO2B_P 0x0154 165*4882a593Smuzhiyun #define RK3288_GRF_GPIO2C_P 0x0158 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define RK3288_GRF_GPIO3A_P 0x0160 168*4882a593Smuzhiyun #define RK3288_GRF_GPIO3B_P 0x0164 169*4882a593Smuzhiyun #define RK3288_GRF_GPIO3C_P 0x0168 170*4882a593Smuzhiyun #define RK3288_GRF_GPIO3D_P 0x016c 171*4882a593Smuzhiyun #define RK3288_GRF_GPIO4A_P 0x0170 172*4882a593Smuzhiyun #define RK3288_GRF_GPIO4B_P 0x0174 173*4882a593Smuzhiyun #define RK3288_GRF_GPIO4C_P 0x0178 174*4882a593Smuzhiyun #define RK3288_GRF_GPIO4D_P 0x017c 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define RK3288_GRF_GPIO5B_P 0x0184 177*4882a593Smuzhiyun #define RK3288_GRF_GPIO5C_P 0x0188 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define RK3288_GRF_GPIO6A_P 0x0190 180*4882a593Smuzhiyun #define RK3288_GRF_GPIO6B_P 0x0194 181*4882a593Smuzhiyun #define RK3288_GRF_GPIO6C_P 0x0198 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define RK3288_GRF_GPIO7A_P 0x01a0 184*4882a593Smuzhiyun #define RK3288_GRF_GPIO7B_P 0x01a4 185*4882a593Smuzhiyun #define RK3288_GRF_GPIO7C_P 0x01a8 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define RK3288_GRF_GPIO8A_P 0x01b0 188*4882a593Smuzhiyun #define RK3288_GRF_GPIO8B_P 0x01b4 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define RK3288_GRF_GPIO1D_E 0x01cc 191*4882a593Smuzhiyun #define RK3288_GRF_GPIO2A_E 0x01d0 192*4882a593Smuzhiyun #define RK3288_GRF_GPIO2B_E 0x01d4 193*4882a593Smuzhiyun #define RK3288_GRF_GPIO2C_E 0x01d8 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #define RK3288_GRF_GPIO3A_E 0x01e0 196*4882a593Smuzhiyun #define RK3288_GRF_GPIO3B_E 0x01e4 197*4882a593Smuzhiyun #define RK3288_GRF_GPIO3C_E 0x01e8 198*4882a593Smuzhiyun #define RK3288_GRF_GPIO3D_E 0x01ec 199*4882a593Smuzhiyun #define RK3288_GRF_GPIO4A_E 0x01f0 200*4882a593Smuzhiyun #define RK3288_GRF_GPIO4B_E 0x01f4 201*4882a593Smuzhiyun #define RK3288_GRF_GPIO4C_E 0x01f8 202*4882a593Smuzhiyun #define RK3288_GRF_GPIO4D_E 0x01fc 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define RK3288_GRF_GPIO5B_E 0x0204 205*4882a593Smuzhiyun #define RK3288_GRF_GPIO5C_E 0x0208 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define RK3288_GRF_GPIO6A_E 0x0210 208*4882a593Smuzhiyun #define RK3288_GRF_GPIO6B_E 0x0214 209*4882a593Smuzhiyun #define RK3288_GRF_GPIO6C_E 0x0218 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun #define RK3288_GRF_GPIO7A_E 0x0220 212*4882a593Smuzhiyun #define RK3288_GRF_GPIO7B_E 0x0224 213*4882a593Smuzhiyun #define RK3288_GRF_GPIO7C_E 0x0228 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #define RK3288_GRF_GPIO8A_E 0x0230 216*4882a593Smuzhiyun #define RK3288_GRF_GPIO8B_E 0x0234 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #define RK3288_GRF_GPIO_SMT 0x0240 219*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON0 0x0244 220*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON1 0x0248 221*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON2 0x024c 222*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON3 0x0250 223*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON4 0x0254 224*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON5 0x0258 225*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON6 0x025c 226*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON7 0x0260 227*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON8 0x0264 228*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON9 0x0268 229*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON10 0x026c 230*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON11 0x0270 231*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON12 0x0274 232*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON13 0x0278 233*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON14 0x027c 234*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS0 0x0280 235*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS1 0x0284 236*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS2 0x0288 237*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS3 0x028c 238*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS4 0x0290 239*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS5 0x0294 240*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS6 0x0298 241*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS7 0x029c 242*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS8 0x02a0 243*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS9 0x02a4 244*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS10 0x02a8 245*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS11 0x02ac 246*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS12 0x02b0 247*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS13 0x02b4 248*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS14 0x02b8 249*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS15 0x02bc 250*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS16 0x02c0 251*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS17 0x02c4 252*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS18 0x02c8 253*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS19 0x02cc 254*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS20 0x02d0 255*4882a593Smuzhiyun #define RK3288_GRF_SOC_STATUS21 0x02d4 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun #define RK3288_GRF_PERIDMAC_CON0 0x02e0 258*4882a593Smuzhiyun #define RK3288_GRF_PERIDMAC_CON1 0x02e4 259*4882a593Smuzhiyun #define RK3288_GRF_PERIDMAC_CON2 0x02e8 260*4882a593Smuzhiyun #define RK3288_GRF_PERIDMAC_CON3 0x02ec 261*4882a593Smuzhiyun #define RK3288_GRF_DDRC0_CON0 0x02f0 262*4882a593Smuzhiyun #define RK3288_GRF_DDRC1_CON0 0x02f4 263*4882a593Smuzhiyun #define RK3288_GRF_CPU_CON0 0x02f8 264*4882a593Smuzhiyun #define RK3288_GRF_CPU_CON1 0x02fc 265*4882a593Smuzhiyun #define RK3288_GRF_CPU_CON2 0x0300 266*4882a593Smuzhiyun #define RK3288_GRF_CPU_CON3 0x0304 267*4882a593Smuzhiyun #define RK3288_GRF_CPU_CON4 0x0308 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun #define RK3288_GRF_CPU_STATUS0 0x0318 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define RK3288_GRF_UOC0_CON0 0x0320 272*4882a593Smuzhiyun #define RK3288_GRF_UOC0_CON1 0x0324 273*4882a593Smuzhiyun #define RK3288_GRF_UOC0_CON2 0x0328 274*4882a593Smuzhiyun #define RK3288_GRF_UOC0_CON3 0x032c 275*4882a593Smuzhiyun #define RK3288_GRF_UOC0_CON4 0x0330 276*4882a593Smuzhiyun #define RK3288_GRF_UOC1_CON0 0x0334 277*4882a593Smuzhiyun #define RK3288_GRF_UOC1_CON1 0x0338 278*4882a593Smuzhiyun #define RK3288_GRF_UOC1_CON2 0x033c 279*4882a593Smuzhiyun #define RK3288_GRF_UOC1_CON3 0x0340 280*4882a593Smuzhiyun #define RK3288_GRF_UOC1_CON4 0x0344 281*4882a593Smuzhiyun #define RK3288_GRF_UOC2_CON0 0x0348 282*4882a593Smuzhiyun #define RK3288_GRF_UOC2_CON1 0x034c 283*4882a593Smuzhiyun #define RK3288_GRF_UOC2_CON2 0x0350 284*4882a593Smuzhiyun #define RK3288_GRF_UOC2_CON3 0x0354 285*4882a593Smuzhiyun #define RK3288_GRF_UOC3_CON0 0x0358 286*4882a593Smuzhiyun #define RK3288_GRF_UOC3_CON1 0x035c 287*4882a593Smuzhiyun #define RK3288_GRF_UOC4_CON0 0x0360 288*4882a593Smuzhiyun #define RK3288_GRF_UOC4_CON1 0x0364 289*4882a593Smuzhiyun #define RK3288_GRF_PVTM_CON0 0x0368 290*4882a593Smuzhiyun #define RK3288_GRF_PVTM_CON1 0x036c 291*4882a593Smuzhiyun #define RK3288_GRF_PVTM_CON2 0x0370 292*4882a593Smuzhiyun #define RK3288_GRF_PVTM_STATUS0 0x0374 293*4882a593Smuzhiyun #define RK3288_GRF_PVTM_STATUS1 0x0378 294*4882a593Smuzhiyun #define RK3288_GRF_PVTM_STATUS2 0x037c 295*4882a593Smuzhiyun #define RK3288_GRF_IO_VSEL 0x0380 296*4882a593Smuzhiyun #define RK3288_GRF_SARADC_TESTBIT 0x0384 297*4882a593Smuzhiyun #define RK3288_GRF_TSADC_TESTBIT_L 0x0388 298*4882a593Smuzhiyun #define RK3288_GRF_TSADC_TESTBIT_H 0x038c 299*4882a593Smuzhiyun #define RK3288_GRF_OS_REG0 0x0390 300*4882a593Smuzhiyun #define RK3288_GRF_OS_REG1 0x0394 301*4882a593Smuzhiyun #define RK3288_GRF_OS_REG2 0x0398 302*4882a593Smuzhiyun #define RK3288_GRF_OS_REG3 0x039c 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON15 0x03a4 305*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON16 0x03a8 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON0 0x0000 308*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON1 0x0004 309*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON2 0x0008 310*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON3 0x000c 311*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON4 0x0010 312*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON5 0x0014 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun #define RK3288_SGRF_BUSDMAC_CON0 0x0020 315*4882a593Smuzhiyun #define RK3288_SGRF_BUSDMAC_CON1 0x0024 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun #define RK3288_SGRF_CPU_CON0 0x0040 318*4882a593Smuzhiyun #define RK3288_SGRF_CPU_CON1 0x0044 319*4882a593Smuzhiyun #define RK3288_SGRF_CPU_CON2 0x0048 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON6 0x0050 322*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON7 0x0054 323*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON8 0x0058 324*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON9 0x005c 325*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON10 0x0060 326*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON11 0x0064 327*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON12 0x0068 328*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON13 0x006c 329*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON14 0x0070 330*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON15 0x0074 331*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON16 0x0078 332*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON17 0x007c 333*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON18 0x0080 334*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON19 0x0084 335*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON20 0x0088 336*4882a593Smuzhiyun #define RK3288_SGRF_SOC_CON21 0x008c 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun #define RK3288_SGRF_SOC_STATUS0 0x0100 339*4882a593Smuzhiyun #define RK3288_SGRF_SOC_STATUS1 0x0104 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun #define RK3288_SGRF_FAST_BOOT_ADDR 0x0120 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define RK3036_GRF_GPIO0A_IOMUX 0x000a8 345*4882a593Smuzhiyun #define RK3036_GRF_GPIO0B_IOMUX 0x000ac 346*4882a593Smuzhiyun #define RK3036_GRF_GPIO0C_IOMUX 0x000b0 347*4882a593Smuzhiyun #define RK3036_GRF_GPIO0D_IOMUX 0x000b4 348*4882a593Smuzhiyun #define RK3036_GRF_GPIO1A_IOMUX 0x000b8 349*4882a593Smuzhiyun #define RK3036_GRF_GPIO1B_IOMUX 0x000bc 350*4882a593Smuzhiyun #define RK3036_GRF_GPIO1C_IOMUX 0x000c0 351*4882a593Smuzhiyun #define RK3036_GRF_GPIO1D_IOMUX 0x000c4 352*4882a593Smuzhiyun #define RK3036_GRF_GPIO2A_IOMUX 0x000c8 353*4882a593Smuzhiyun #define RK3036_GRF_GPIO2B_IOMUX 0x000cc 354*4882a593Smuzhiyun #define RK3036_GRF_GPIO2C_IOMUX 0x000d0 355*4882a593Smuzhiyun #define RK3036_GRF_GPIO2D_IOMUX 0x000d4 356*4882a593Smuzhiyun #define RK3036_GRF_GPIO_DS 0x00100 357*4882a593Smuzhiyun #define RK3036_GRF_GPIO0L_PULL 0x00118 358*4882a593Smuzhiyun #define RK3036_GRF_GPIO0H_PULL 0x0011c 359*4882a593Smuzhiyun #define RK3036_GRF_GPIO1L_PULL 0x00120 360*4882a593Smuzhiyun #define RK3036_GRF_GPIO1H_PULL 0x00124 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun #define RK3036_GRF_GPIO2L_PULL 0x00128 363*4882a593Smuzhiyun #define RK3036_GRF_GPIO2H_PULL 0x0012c 364*4882a593Smuzhiyun #define RK3036_GRF_SOC_CON0 0x00140 365*4882a593Smuzhiyun #define RK3036_GRF_SOC_CON1 0x00144 366*4882a593Smuzhiyun #define RK3036_GRF_SOC_CON2 0x00148 367*4882a593Smuzhiyun #define RK3036_GRF_SOC_STATUS0 0x0014c 368*4882a593Smuzhiyun #define RK3036_GRF_SOC_CON3 0x00154 369*4882a593Smuzhiyun #define RK3036_GRF_DMAC_CON0 0x0015c 370*4882a593Smuzhiyun #define RK3036_GRF_DMAC_CON1 0x00160 371*4882a593Smuzhiyun #define RK3036_GRF_DMAC_CON2 0x00164 372*4882a593Smuzhiyun #define RK3036_GRF_UOC0_CON5 0x0017c 373*4882a593Smuzhiyun #define RK3036_GRF_UOC1_CON4 0x00190 374*4882a593Smuzhiyun #define RK3036_GRF_UOC1_CON5 0x00194 375*4882a593Smuzhiyun #define RK3036_GRF_DDRC_STAT 0x0019c 376*4882a593Smuzhiyun #define RK3036_GRF_UOC_CON6 0x001a0 377*4882a593Smuzhiyun #define RK3036_GRF_SOC_STATUS1 0x001a4 378*4882a593Smuzhiyun #define RK3036_GRF_CPU_CON0 0x001a8 379*4882a593Smuzhiyun #define RK3036_GRF_CPU_CON1 0x001ac 380*4882a593Smuzhiyun #define RK3036_GRF_CPU_CON2 0x001b0 381*4882a593Smuzhiyun #define RK3036_GRF_CPU_CON3 0x001b4 382*4882a593Smuzhiyun #define RK3036_GRF_CPU_STATUS0 0x001c0 383*4882a593Smuzhiyun #define RK3036_GRF_CPU_STATUS1 0x001c4 384*4882a593Smuzhiyun #define RK3036_GRF_OS_REG0 0x001c8 385*4882a593Smuzhiyun #define RK3036_GRF_OS_REG1 0x001cc 386*4882a593Smuzhiyun #define RK3036_GRF_OS_REG2 0x001d0 387*4882a593Smuzhiyun #define RK3036_GRF_OS_REG3 0x001d4 388*4882a593Smuzhiyun #define RK3036_GRF_OS_REG4 0x001d8 389*4882a593Smuzhiyun #define RK3036_GRF_OS_REG5 0x001dc 390*4882a593Smuzhiyun #define RK3036_GRF_OS_REG6 0x001e0 391*4882a593Smuzhiyun #define RK3036_GRF_OS_REG7 0x001e4 392*4882a593Smuzhiyun #define RK3036_GRF_DLL_CON0 0x00200 393*4882a593Smuzhiyun #define RK3036_GRF_DLL_CON1 0x00204 394*4882a593Smuzhiyun #define RK3036_GRF_DLL_CON2 0x00208 395*4882a593Smuzhiyun #define RK3036_GRF_DLL_CON3 0x0020c 396*4882a593Smuzhiyun #define RK3036_GRF_DLL_STATUS0 0x00210 397*4882a593Smuzhiyun #define RK3036_GRF_DLL_STATUS1 0x00214 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun #define RK3036_GRF_DLL_STATUS2 0x00218 400*4882a593Smuzhiyun #define RK3036_GRF_DLL_STATUS3 0x0021c 401*4882a593Smuzhiyun #define RK3036_GRF_DFI_WRNUM 0x00220 402*4882a593Smuzhiyun #define RK3036_GRF_DFI_RDNUM 0x00224 403*4882a593Smuzhiyun #define RK3036_GRF_DFI_ACTNUM 0x00228 404*4882a593Smuzhiyun #define RK3036_GRF_DFI_TIMERVAL 0x0022c 405*4882a593Smuzhiyun #define RK3036_GRF_NIF_FIFO0 0x00230 406*4882a593Smuzhiyun #define RK3036_GRF_NIF_FIFO1 0x00234 407*4882a593Smuzhiyun #define RK3036_GRF_NIF_FIFO2 0x00238 408*4882a593Smuzhiyun #define RK3036_GRF_NIF_FIFO3 0x0023c 409*4882a593Smuzhiyun #define RK3036_GRF_USBPHY0_CON0 0x00280 410*4882a593Smuzhiyun #define RK3036_GRF_USBPHY0_CON1 0x00284 411*4882a593Smuzhiyun #define RK3036_GRF_USBPHY0_CON2 0x00288 412*4882a593Smuzhiyun #define RK3036_GRF_USBPHY0_CON3 0x0028c 413*4882a593Smuzhiyun #define RK3036_GRF_USBPHY0_CON4 0x00290 414*4882a593Smuzhiyun #define RK3036_GRF_USBPHY0_CON5 0x00294 415*4882a593Smuzhiyun #define RK3036_GRF_USBPHY0_CON6 0x00298 416*4882a593Smuzhiyun #define RK3036_GRF_USBPHY0_CON7 0x0029c 417*4882a593Smuzhiyun #define RK3036_GRF_USBPHY1_CON0 0x002a0 418*4882a593Smuzhiyun #define RK3036_GRF_USBPHY1_CON1 0x002a4 419*4882a593Smuzhiyun #define RK3036_GRF_USBPHY1_CON2 0x002a8 420*4882a593Smuzhiyun #define RK3036_GRF_USBPHY1_CON3 0x002ac 421*4882a593Smuzhiyun #define RK3036_GRF_USBPHY1_CON4 0x002b0 422*4882a593Smuzhiyun #define RK3036_GRF_USBPHY1_CON5 0x002b4 423*4882a593Smuzhiyun #define RK3036_GRF_USBPHY1_CON6 0x002b8 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun #define RK3036_GRF_USBPHY1_CON7 0x002bc 426*4882a593Smuzhiyun #define RK3036_GRF_CHIP_TAG 0x00300 427*4882a593Smuzhiyun #define RK3036_GRF_SDMMC_DET_CNT 0x00304 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun #define RK312X_GRF_GPIO0A_IOMUX 0x000a8 430*4882a593Smuzhiyun #define RK312X_GRF_GPIO0B_IOMUX 0x000ac 431*4882a593Smuzhiyun #define RK312X_GRF_GPIO0C_IOMUX 0x000b0 432*4882a593Smuzhiyun #define RK312X_GRF_GPIO0D_IOMUX 0x000b4 433*4882a593Smuzhiyun #define RK312X_GRF_GPIO1A_IOMUX 0x000b8 434*4882a593Smuzhiyun #define RK312X_GRF_GPIO1B_IOMUX 0x000bc 435*4882a593Smuzhiyun #define RK312X_GRF_GPIO1C_IOMUX 0x000c0 436*4882a593Smuzhiyun #define RK312X_GRF_GPIO1D_IOMUX 0x000c4 437*4882a593Smuzhiyun #define RK312X_GRF_GPIO2A_IOMUX 0x000c8 438*4882a593Smuzhiyun #define RK312X_GRF_GPIO2B_IOMUX 0x000cc 439*4882a593Smuzhiyun #define RK312X_GRF_GPIO2C_IOMUX 0x000d0 440*4882a593Smuzhiyun #define RK312X_GRF_GPIO2D_IOMUX 0x000d4 441*4882a593Smuzhiyun #define RK312X_GRF_GPIO3A_IOMUX 0x000d8 442*4882a593Smuzhiyun #define RK312X_GRF_GPIO3B_IOMUX 0x000dc 443*4882a593Smuzhiyun #define RK312X_GRF_GPIO3C_IOMUX 0x000e0 444*4882a593Smuzhiyun #define RK312X_GRF_GPIO3D_IOMUX 0x000e4 445*4882a593Smuzhiyun #define RK312X_GRF_CIF_IOMUX 0x000ec 446*4882a593Smuzhiyun #define RK312X_GRF_CIF_IOMUX1 0x000f0 447*4882a593Smuzhiyun #define RK312X_GRF_GPIO_DS 0x00100 448*4882a593Smuzhiyun #define RK312X_GRF_GPIO0L_PULL 0x00118 449*4882a593Smuzhiyun #define RK312X_GRF_GPIO0H_PULL 0x0011c 450*4882a593Smuzhiyun #define RK312X_GRF_GPIO1L_PULL 0x00120 451*4882a593Smuzhiyun #define RK312X_GRF_GPIO1H_PULL 0x00124 452*4882a593Smuzhiyun #define RK312X_GRF_GPIO2L_PULL 0x00128 453*4882a593Smuzhiyun #define RK312X_GRF_GPIO2H_PULL 0x0012c 454*4882a593Smuzhiyun #define RK312X_GRF_GPIO3L_PULL 0x00130 455*4882a593Smuzhiyun #define RK312X_GRF_GPIO3H_PULL 0x00134 456*4882a593Smuzhiyun #define RK312X_GRF_ACODEC_CON 0x0013c 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun #define RK312X_GRF_SOC_CON0 0x00140 459*4882a593Smuzhiyun #define RK312X_GRF_SOC_CON1 0x00144 460*4882a593Smuzhiyun #define RK312X_GRF_SOC_CON2 0x00148 461*4882a593Smuzhiyun #define RK312X_GRF_SOC_STATUS0 0x0014c 462*4882a593Smuzhiyun #define RK312X_GRF_LVDS_CON0 0x00150 463*4882a593Smuzhiyun #define RK312X_GRF_SOC_CON3 0x00154 464*4882a593Smuzhiyun #define RK312X_GRF_DMAC_CON0 0x0015c 465*4882a593Smuzhiyun #define RK312X_GRF_DMAC_CON1 0x00160 466*4882a593Smuzhiyun #define RK312X_GRF_DMAC_CON2 0x00164 467*4882a593Smuzhiyun #define RK312X_GRF_MAC_CON0 0x00168 468*4882a593Smuzhiyun #define RK312X_GRF_MAC_CON1 0x0016c 469*4882a593Smuzhiyun #define RK312X_GRF_TVE_CON 0x00170 470*4882a593Smuzhiyun #define RK312X_GRF_UOC0_CON0 0x0017c 471*4882a593Smuzhiyun #define RK312X_GRF_UOC1_CON1 0x00184 472*4882a593Smuzhiyun #define RK312X_GRF_UOC1_CON2 0x00188 473*4882a593Smuzhiyun #define RK312X_GRF_UOC1_CON3 0x0018c 474*4882a593Smuzhiyun #define RK312X_GRF_UOC1_CON4 0x00190 475*4882a593Smuzhiyun #define RK312X_GRF_UOC1_CON5 0x00194 476*4882a593Smuzhiyun #define RK312X_GRF_DDRC_STAT 0x0019c 477*4882a593Smuzhiyun #define RK312X_GRF_SOC_STATUS1 0x001a4 478*4882a593Smuzhiyun #define RK312X_GRF_CPU_CON0 0x001a8 479*4882a593Smuzhiyun #define RK312X_GRF_CPU_CON1 0x001ac 480*4882a593Smuzhiyun #define RK312X_GRF_CPU_CON2 0x001b0 481*4882a593Smuzhiyun #define RK312X_GRF_CPU_CON3 0x001b4 482*4882a593Smuzhiyun #define RK312X_GRF_CPU_STATUS0 0x001c0 483*4882a593Smuzhiyun #define RK312X_GRF_CPU_STATUS1 0x001c4 484*4882a593Smuzhiyun #define RK312X_GRF_OS_REG0 0x001c8 485*4882a593Smuzhiyun #define RK312X_GRF_OS_REG1 0x001cc 486*4882a593Smuzhiyun #define RK312X_GRF_OS_REG2 0x001d0 487*4882a593Smuzhiyun #define RK312X_GRF_OS_REG3 0x001d4 488*4882a593Smuzhiyun #define RK312X_GRF_OS_REG4 0x001d8 489*4882a593Smuzhiyun #define RK312X_GRF_OS_REG5 0x001dc 490*4882a593Smuzhiyun #define RK312X_GRF_OS_REG6 0x001e0 491*4882a593Smuzhiyun #define RK312X_GRF_OS_REG7 0x001e4 492*4882a593Smuzhiyun #define RK312X_GRF_PVTM_CON0 0x00200 493*4882a593Smuzhiyun #define RK312X_GRF_PVTM_CON1 0x00204 494*4882a593Smuzhiyun #define RK312X_GRF_PVTM_CON2 0x00208 495*4882a593Smuzhiyun #define RK312X_GRF_PVTM_CON3 0x0020c 496*4882a593Smuzhiyun #define RK312X_GRF_PVTM_STATUS0 0x00210 497*4882a593Smuzhiyun #define RK312X_GRF_PVTM_STATUS1 0x00214 498*4882a593Smuzhiyun #define RK312X_GRF_PVTM_STATUS2 0x00218 499*4882a593Smuzhiyun #define RK312X_GRF_PVTM_STATUS3 0x0021c 500*4882a593Smuzhiyun #define RK312X_GRF_DFI_WRNUM 0x00220 501*4882a593Smuzhiyun #define RK312X_GRF_DFI_RDNUM 0x00224 502*4882a593Smuzhiyun #define RK312X_GRF_DFI_ACTNUM 0x00228 503*4882a593Smuzhiyun #define RK312X_GRF_DFI_TIMERVAL 0x0022c 504*4882a593Smuzhiyun #define RK312X_GRF_NIF_FIFO0 0x00230 505*4882a593Smuzhiyun #define RK312X_GRF_NIF_FIFO1 0x00234 506*4882a593Smuzhiyun #define RK312X_GRF_NIF_FIFO2 0x00238 507*4882a593Smuzhiyun #define RK312X_GRF_NIF_FIFO3 0x0023c 508*4882a593Smuzhiyun #define RK312X_GRF_USBPHY0_CON0 0x00280 509*4882a593Smuzhiyun #define RK312X_GRF_USBPHY0_CON1 0x00284 510*4882a593Smuzhiyun #define RK312X_GRF_USBPHY0_CON2 0x00288 511*4882a593Smuzhiyun #define RK312X_GRF_USBPHY0_CON3 0x0028c 512*4882a593Smuzhiyun #define RK312X_GRF_USBPHY0_CON4 0x00290 513*4882a593Smuzhiyun #define RK312X_GRF_USBPHY0_CON5 0x00294 514*4882a593Smuzhiyun #define RK312X_GRF_USBPHY0_CON6 0x00298 515*4882a593Smuzhiyun #define RK312X_GRF_USBPHY0_CON7 0x0029c 516*4882a593Smuzhiyun #define RK312X_GRF_USBPHY1_CON0 0x002a0 517*4882a593Smuzhiyun #define RK312X_GRF_USBPHY1_CON1 0x002a4 518*4882a593Smuzhiyun #define RK312X_GRF_USBPHY1_CON2 0x002a8 519*4882a593Smuzhiyun #define RK312X_GRF_USBPHY1_CON3 0x002ac 520*4882a593Smuzhiyun #define RK312X_GRF_USBPHY1_CON4 0x002b0 521*4882a593Smuzhiyun #define RK312X_GRF_USBPHY1_CON5 0x002b4 522*4882a593Smuzhiyun #define RK312X_GRF_USBPHY1_CON6 0x002b8 523*4882a593Smuzhiyun #define RK312X_GRF_USBPHY1_CON7 0x002bc 524*4882a593Smuzhiyun #define RK312X_GRF_UOC_STATUS0 0x002c0 525*4882a593Smuzhiyun #define RK312X_GRF_CHIP_TAG 0x00300 526*4882a593Smuzhiyun #define RK312X_GRF_SDMMC_DET_CNT 0x00304 527*4882a593Smuzhiyun #define RK312X_GRF_EFUSE_PRG_EN 0x0037c 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun #define RK3228_GRF_GPIO0A_IOMUX 0x0000 530*4882a593Smuzhiyun #define RK3228_GRF_GPIO0B_IOMUX 0x0004 531*4882a593Smuzhiyun #define RK3228_GRF_GPIO0C_IOMUX 0x0008 532*4882a593Smuzhiyun #define RK3228_GRF_GPIO0D_IOMUX 0x000c 533*4882a593Smuzhiyun #define RK3228_GRF_GPIO1A_IOMUX 0x0010 534*4882a593Smuzhiyun #define RK3228_GRF_GPIO1B_IOMUX 0x0014 535*4882a593Smuzhiyun #define RK3228_GRF_GPIO1C_IOMUX 0x0018 536*4882a593Smuzhiyun #define RK3228_GRF_GPIO1D_IOMUX 0x001c 537*4882a593Smuzhiyun #define RK3228_GRF_GPIO2A_IOMUX 0x0020 538*4882a593Smuzhiyun #define RK3228_GRF_GPIO2B_IOMUX 0x0024 539*4882a593Smuzhiyun #define RK3228_GRF_GPIO2C_IOMUX 0x0028 540*4882a593Smuzhiyun #define RK3228_GRF_GPIO2D_IOMUX 0x002c 541*4882a593Smuzhiyun #define RK3228_GRF_GPIO3A_IOMUX 0x0030 542*4882a593Smuzhiyun #define RK3228_GRF_GPIO3B_IOMUX 0x0034 543*4882a593Smuzhiyun #define RK3228_GRF_GPIO3C_IOMUX 0x0038 544*4882a593Smuzhiyun #define RK3228_GRF_GPIO3D_IOMUX 0x003c 545*4882a593Smuzhiyun #define RK3228_GRF_COM_IOMUX 0x0050 546*4882a593Smuzhiyun #define RK3228_GRF_GPIO0A_P 0x0100 547*4882a593Smuzhiyun #define RK3228_GRF_GPIO0B_P 0x0104 548*4882a593Smuzhiyun #define RK3228_GRF_GPIO0C_P 0x0108 549*4882a593Smuzhiyun #define RK3228_GRF_GPIO0D_P 0x010c 550*4882a593Smuzhiyun #define RK3228_GRF_GPIO1A_P 0x0110 551*4882a593Smuzhiyun #define RK3228_GRF_GPIO1B_P 0x0114 552*4882a593Smuzhiyun #define RK3228_GRF_GPIO1C_P 0x0118 553*4882a593Smuzhiyun #define RK3228_GRF_GPIO1D_P 0x011c 554*4882a593Smuzhiyun #define RK3228_GRF_GPIO2A_P 0x0120 555*4882a593Smuzhiyun #define RK3228_GRF_GPIO2B_P 0x0124 556*4882a593Smuzhiyun #define RK3228_GRF_GPIO2C_P 0x0128 557*4882a593Smuzhiyun #define RK3228_GRF_GPIO2D_P 0x012c 558*4882a593Smuzhiyun #define RK3228_GRF_GPIO3A_P 0x0130 559*4882a593Smuzhiyun #define RK3228_GRF_GPIO3B_P 0x0134 560*4882a593Smuzhiyun #define RK3228_GRF_GPIO3C_P 0x0138 561*4882a593Smuzhiyun #define RK3228_GRF_GPIO3D_P 0x013c 562*4882a593Smuzhiyun #define RK3228_GRF_GPIO0A_E 0x0200 563*4882a593Smuzhiyun #define RK3228_GRF_GPIO0B_E 0x0204 564*4882a593Smuzhiyun #define RK3228_GRF_GPIO0C_E 0x0208 565*4882a593Smuzhiyun #define RK3228_GRF_GPIO0D_E 0x020c 566*4882a593Smuzhiyun #define RK3228_GRF_GPIO1A_E 0x0210 567*4882a593Smuzhiyun #define RK3228_GRF_GPIO1B_E 0x0214 568*4882a593Smuzhiyun #define RK3228_GRF_GPIO1C_E 0x0218 569*4882a593Smuzhiyun #define RK3228_GRF_GPIO1D_E 0x021c 570*4882a593Smuzhiyun #define RK3228_GRF_GPIO2A_E 0x0220 571*4882a593Smuzhiyun #define RK3228_GRF_GPIO2B_E 0x0224 572*4882a593Smuzhiyun #define RK3228_GRF_GPIO2C_E 0x0228 573*4882a593Smuzhiyun #define RK3228_GRF_GPIO2D_E 0x022c 574*4882a593Smuzhiyun #define RK3228_GRF_GPIO3A_E 0x0230 575*4882a593Smuzhiyun #define RK3228_GRF_GPIO3B_E 0x0234 576*4882a593Smuzhiyun #define RK3228_GRF_GPIO3C_E 0x0238 577*4882a593Smuzhiyun #define RK3228_GRF_GPIO3D_E 0x023c 578*4882a593Smuzhiyun #define RK3228_GRF_GPIO0L_SR 0x0300 579*4882a593Smuzhiyun #define RK3228_GRF_GPIO0H_SR 0x0304 580*4882a593Smuzhiyun #define RK3228_GRF_GPIO1L_SR 0x0308 581*4882a593Smuzhiyun #define RK3228_GRF_GPIO1H_SR 0x030c 582*4882a593Smuzhiyun #define RK3228_GRF_GPIO2L_SR 0x0310 583*4882a593Smuzhiyun #define RK3228_GRF_GPIO2H_SR 0x0314 584*4882a593Smuzhiyun #define RK3228_GRF_GPIO3L_SR 0x0318 585*4882a593Smuzhiyun #define RK3228_GRF_GPIO3H_SR 0x031c 586*4882a593Smuzhiyun #define RK3228_GRF_GPIO0L_SMT 0x0380 587*4882a593Smuzhiyun #define RK3228_GRF_GPIO0H_SMT 0x0384 588*4882a593Smuzhiyun #define RK3228_GRF_GPIO1L_SMT 0x0388 589*4882a593Smuzhiyun #define RK3228_GRF_GPIO1H_SMT 0x038c 590*4882a593Smuzhiyun #define RK3228_GRF_GPIO2L_SMT 0x0390 591*4882a593Smuzhiyun #define RK3228_GRF_GPIO2H_SMT 0x0394 592*4882a593Smuzhiyun #define RK3228_GRF_GPIO3L_SMT 0x0398 593*4882a593Smuzhiyun #define RK3228_GRF_GPIO3H_SMT 0x039c 594*4882a593Smuzhiyun #define RK3228_GRF_SOC_CON0 0x0400 595*4882a593Smuzhiyun #define RK3228_GRF_SOC_CON1 0x0404 596*4882a593Smuzhiyun #define RK3228_GRF_SOC_CON2 0x0408 597*4882a593Smuzhiyun #define RK3228_GRF_SOC_CON3 0x040c 598*4882a593Smuzhiyun #define RK3228_GRF_SOC_CON4 0x0410 599*4882a593Smuzhiyun #define RK3228_GRF_SOC_CON5 0x0414 600*4882a593Smuzhiyun #define RK3228_GRF_SOC_CON6 0x0418 601*4882a593Smuzhiyun #define RK3228_GRF_SOC_STATUS0 0x0480 602*4882a593Smuzhiyun #define RK3228_GRF_SOC_STATUS1 0x0484 603*4882a593Smuzhiyun #define RK3228_GRF_SOC_STATUS2 0x0488 604*4882a593Smuzhiyun #define RK3228_GRF_CHIP_ID 0x048c 605*4882a593Smuzhiyun #define RK3228_GRF_CPU_CON0 0x0500 606*4882a593Smuzhiyun #define RK3228_GRF_CPU_CON1 0x0504 607*4882a593Smuzhiyun #define RK3228_GRF_CPU_CON2 0x0508 608*4882a593Smuzhiyun #define RK3228_GRF_CPU_CON3 0x050c 609*4882a593Smuzhiyun #define RK3228_GRF_CPU_STATUS0 0x0520 610*4882a593Smuzhiyun #define RK3228_GRF_CPU_STATUS1 0x0524 611*4882a593Smuzhiyun #define RK3228_GRF_OS_REG0 0x05c8 612*4882a593Smuzhiyun #define RK3228_GRF_OS_REG1 0x05cc 613*4882a593Smuzhiyun #define RK3228_GRF_OS_REG2 0x05d0 614*4882a593Smuzhiyun #define RK3228_GRF_OS_REG3 0x05d4 615*4882a593Smuzhiyun #define RK3228_GRF_OS_REG4 0x05d8 616*4882a593Smuzhiyun #define RK3228_GRF_OS_REG5 0x05dc 617*4882a593Smuzhiyun #define RK3228_GRF_OS_REG6 0x05e0 618*4882a593Smuzhiyun #define RK3228_GRF_OS_REG7 0x05e4 619*4882a593Smuzhiyun #define RK3228_GRF_DDRC_STAT 0x0604 620*4882a593Smuzhiyun #define RK3228_GRF_SIG_DETECT_CON 0x0680 621*4882a593Smuzhiyun #define RK3228_GRF_SIG_DETECT_CON1 0x0684 622*4882a593Smuzhiyun #define RK3228_GRF_SIG_DETECT_STATUS 0x0690 623*4882a593Smuzhiyun #define RK3228_GRF_SIG_DETECT_STATUS1 0x0694 624*4882a593Smuzhiyun #define RK3228_GRF_SIG_DETECT_CLR 0x06a0 625*4882a593Smuzhiyun #define RK3228_GRF_SIG_DETECT_CLR1 0x06a4 626*4882a593Smuzhiyun #define RK3228_GRF_EMMC_DET 0x06b0 627*4882a593Smuzhiyun #define RK3228_GRF_HOST0_CON0 0x0700 628*4882a593Smuzhiyun #define RK3228_GRF_HOST0_CON1 0x0704 629*4882a593Smuzhiyun #define RK3228_GRF_HOST0_CON2 0x0708 630*4882a593Smuzhiyun #define RK3228_GRF_HOST1_CON0 0x0710 631*4882a593Smuzhiyun #define RK3228_GRF_HOST1_CON1 0x0714 632*4882a593Smuzhiyun #define RK3228_GRF_HOST1_CON2 0x0718 633*4882a593Smuzhiyun #define RK3228_GRF_HOST2_CON0 0x0720 634*4882a593Smuzhiyun #define RK3228_GRF_HOST2_CON1 0x0724 635*4882a593Smuzhiyun #define RK3228_GRF_HOST2_CON2 0x0728 636*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON0 0x0760 637*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON1 0x0764 638*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON2 0x0768 639*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON3 0x076c 640*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON4 0x0770 641*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON5 0x0774 642*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON6 0x0778 643*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON7 0x077c 644*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON8 0x0780 645*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON9 0x0784 646*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON10 0x0788 647*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON11 0x078c 648*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON12 0x0790 649*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON13 0x0794 650*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON14 0x0798 651*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON15 0x079c 652*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON16 0x07a0 653*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON17 0x07a4 654*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON18 0x07a8 655*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON19 0x07ac 656*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON20 0x07b0 657*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON21 0x07b4 658*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON22 0x07b8 659*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON23 0x07bc 660*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON24 0x07c0 661*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON25 0x07c4 662*4882a593Smuzhiyun #define RK3228_GRF_USBPHY0_CON26 0x07c8 663*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON0 0x0800 664*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON1 0x0804 665*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON2 0x0808 666*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON3 0x080c 667*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON4 0x0810 668*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON5 0x0814 669*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON6 0x0818 670*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON7 0x081c 671*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON8 0x0820 672*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON9 0x0824 673*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON10 0x0828 674*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON11 0x082c 675*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON12 0x0830 676*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON13 0x0834 677*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON14 0x0838 678*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON15 0x083c 679*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON16 0x0840 680*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON17 0x0844 681*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON18 0x0848 682*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON19 0x084c 683*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON20 0x0850 684*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON21 0x0854 685*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON22 0x0858 686*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON23 0x085c 687*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON24 0x0860 688*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON25 0x0864 689*4882a593Smuzhiyun #define RK3228_GRF_USBPHY1_CON26 0x0868 690*4882a593Smuzhiyun #define RK3228_GRF_OTG_CON0 0x0880 691*4882a593Smuzhiyun #define RK3228_GRF_UOC_CON0 0x0884 692*4882a593Smuzhiyun #define RK3228_GRF_MAC_CON0 0x0900 693*4882a593Smuzhiyun #define RK3228_GRF_MAC_CON1 0x0904 694*4882a593Smuzhiyun #define RK3228_GRF_MACPHY_CON0 0x0b00 695*4882a593Smuzhiyun #define RK3228_GRF_MACPHY_CON1 0x0b04 696*4882a593Smuzhiyun #define RK3228_GRF_MACPHY_CON2 0x0b08 697*4882a593Smuzhiyun #define RK3228_GRF_MACPHY_CON3 0x0b0c 698*4882a593Smuzhiyun #define RK3228_GRF_MACPHY_STATUS 0x0b10 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun #endif 701