1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Simple Reset Controller ops 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Based on Allwinner SoCs Reset Controller driver 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright 2013 Maxime Ripard 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __RESET_SIMPLE_H__ 13*4882a593Smuzhiyun #define __RESET_SIMPLE_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/io.h> 16*4882a593Smuzhiyun #include <linux/reset-controller.h> 17*4882a593Smuzhiyun #include <linux/spinlock.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /** 20*4882a593Smuzhiyun * struct reset_simple_data - driver data for simple reset controllers 21*4882a593Smuzhiyun * @lock: spinlock to protect registers during read-modify-write cycles 22*4882a593Smuzhiyun * @membase: memory mapped I/O register range 23*4882a593Smuzhiyun * @rcdev: reset controller device base structure 24*4882a593Smuzhiyun * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits 25*4882a593Smuzhiyun * are set to assert the reset. Note that this says nothing about 26*4882a593Smuzhiyun * the voltage level of the actual reset line. 27*4882a593Smuzhiyun * @status_active_low: if true, bits read back as cleared while the reset is 28*4882a593Smuzhiyun * asserted. Otherwise, bits read back as set while the 29*4882a593Smuzhiyun * reset is asserted. 30*4882a593Smuzhiyun * @reset_us: Minimum delay in microseconds needed that needs to be 31*4882a593Smuzhiyun * waited for between an assert and a deassert to reset the 32*4882a593Smuzhiyun * device. If multiple consumers with different delay 33*4882a593Smuzhiyun * requirements are connected to this controller, it must 34*4882a593Smuzhiyun * be the largest minimum delay. 0 means that such a delay is 35*4882a593Smuzhiyun * unknown and the reset operation is unsupported. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun struct reset_simple_data { 38*4882a593Smuzhiyun spinlock_t lock; 39*4882a593Smuzhiyun void __iomem *membase; 40*4882a593Smuzhiyun struct reset_controller_dev rcdev; 41*4882a593Smuzhiyun bool active_low; 42*4882a593Smuzhiyun bool status_active_low; 43*4882a593Smuzhiyun unsigned int reset_us; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun extern const struct reset_control_ops reset_simple_ops; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* __RESET_SIMPLE_H__ */ 49