1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __LINUX_REG_PFUZE100_H 6*4882a593Smuzhiyun #define __LINUX_REG_PFUZE100_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define PFUZE100_SW1AB 0 9*4882a593Smuzhiyun #define PFUZE100_SW1C 1 10*4882a593Smuzhiyun #define PFUZE100_SW2 2 11*4882a593Smuzhiyun #define PFUZE100_SW3A 3 12*4882a593Smuzhiyun #define PFUZE100_SW3B 4 13*4882a593Smuzhiyun #define PFUZE100_SW4 5 14*4882a593Smuzhiyun #define PFUZE100_SWBST 6 15*4882a593Smuzhiyun #define PFUZE100_VSNVS 7 16*4882a593Smuzhiyun #define PFUZE100_VREFDDR 8 17*4882a593Smuzhiyun #define PFUZE100_VGEN1 9 18*4882a593Smuzhiyun #define PFUZE100_VGEN2 10 19*4882a593Smuzhiyun #define PFUZE100_VGEN3 11 20*4882a593Smuzhiyun #define PFUZE100_VGEN4 12 21*4882a593Smuzhiyun #define PFUZE100_VGEN5 13 22*4882a593Smuzhiyun #define PFUZE100_VGEN6 14 23*4882a593Smuzhiyun #define PFUZE100_COIN 15 24*4882a593Smuzhiyun #define PFUZE100_MAX_REGULATOR 16 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define PFUZE200_SW1AB 0 27*4882a593Smuzhiyun #define PFUZE200_SW2 1 28*4882a593Smuzhiyun #define PFUZE200_SW3A 2 29*4882a593Smuzhiyun #define PFUZE200_SW3B 3 30*4882a593Smuzhiyun #define PFUZE200_SWBST 4 31*4882a593Smuzhiyun #define PFUZE200_VSNVS 5 32*4882a593Smuzhiyun #define PFUZE200_VREFDDR 6 33*4882a593Smuzhiyun #define PFUZE200_VGEN1 7 34*4882a593Smuzhiyun #define PFUZE200_VGEN2 8 35*4882a593Smuzhiyun #define PFUZE200_VGEN3 9 36*4882a593Smuzhiyun #define PFUZE200_VGEN4 10 37*4882a593Smuzhiyun #define PFUZE200_VGEN5 11 38*4882a593Smuzhiyun #define PFUZE200_VGEN6 12 39*4882a593Smuzhiyun #define PFUZE200_COIN 13 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define PFUZE3000_SW1A 0 42*4882a593Smuzhiyun #define PFUZE3000_SW1B 1 43*4882a593Smuzhiyun #define PFUZE3000_SW2 2 44*4882a593Smuzhiyun #define PFUZE3000_SW3 3 45*4882a593Smuzhiyun #define PFUZE3000_SWBST 4 46*4882a593Smuzhiyun #define PFUZE3000_VSNVS 5 47*4882a593Smuzhiyun #define PFUZE3000_VREFDDR 6 48*4882a593Smuzhiyun #define PFUZE3000_VLDO1 7 49*4882a593Smuzhiyun #define PFUZE3000_VLDO2 8 50*4882a593Smuzhiyun #define PFUZE3000_VCCSD 9 51*4882a593Smuzhiyun #define PFUZE3000_V33 10 52*4882a593Smuzhiyun #define PFUZE3000_VLDO3 11 53*4882a593Smuzhiyun #define PFUZE3000_VLDO4 12 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define PFUZE3001_SW1 0 56*4882a593Smuzhiyun #define PFUZE3001_SW2 1 57*4882a593Smuzhiyun #define PFUZE3001_SW3 2 58*4882a593Smuzhiyun #define PFUZE3001_VSNVS 3 59*4882a593Smuzhiyun #define PFUZE3001_VLDO1 4 60*4882a593Smuzhiyun #define PFUZE3001_VLDO2 5 61*4882a593Smuzhiyun #define PFUZE3001_VCCSD 6 62*4882a593Smuzhiyun #define PFUZE3001_V33 7 63*4882a593Smuzhiyun #define PFUZE3001_VLDO3 8 64*4882a593Smuzhiyun #define PFUZE3001_VLDO4 9 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct regulator_init_data; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct pfuze_regulator_platform_data { 69*4882a593Smuzhiyun struct regulator_init_data *init_data[PFUZE100_MAX_REGULATOR]; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __LINUX_REG_PFUZE100_H */ 73