1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Flora Fu <flora.fu@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LINUX_REGULATOR_MT6397_H 8*4882a593Smuzhiyun #define __LINUX_REGULATOR_MT6397_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun enum { 11*4882a593Smuzhiyun MT6397_ID_VPCA15 = 0, 12*4882a593Smuzhiyun MT6397_ID_VPCA7, 13*4882a593Smuzhiyun MT6397_ID_VSRAMCA15, 14*4882a593Smuzhiyun MT6397_ID_VSRAMCA7, 15*4882a593Smuzhiyun MT6397_ID_VCORE, 16*4882a593Smuzhiyun MT6397_ID_VGPU, 17*4882a593Smuzhiyun MT6397_ID_VDRM, 18*4882a593Smuzhiyun MT6397_ID_VIO18 = 7, 19*4882a593Smuzhiyun MT6397_ID_VTCXO, 20*4882a593Smuzhiyun MT6397_ID_VA28, 21*4882a593Smuzhiyun MT6397_ID_VCAMA, 22*4882a593Smuzhiyun MT6397_ID_VIO28, 23*4882a593Smuzhiyun MT6397_ID_VUSB, 24*4882a593Smuzhiyun MT6397_ID_VMC, 25*4882a593Smuzhiyun MT6397_ID_VMCH, 26*4882a593Smuzhiyun MT6397_ID_VEMC3V3, 27*4882a593Smuzhiyun MT6397_ID_VGP1, 28*4882a593Smuzhiyun MT6397_ID_VGP2, 29*4882a593Smuzhiyun MT6397_ID_VGP3, 30*4882a593Smuzhiyun MT6397_ID_VGP4, 31*4882a593Smuzhiyun MT6397_ID_VGP5, 32*4882a593Smuzhiyun MT6397_ID_VGP6, 33*4882a593Smuzhiyun MT6397_ID_VIBR, 34*4882a593Smuzhiyun MT6397_ID_RG_MAX, 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define MT6397_MAX_REGULATOR MT6397_ID_RG_MAX 38*4882a593Smuzhiyun #define MT6397_REGULATOR_ID97 0x97 39*4882a593Smuzhiyun #define MT6397_REGULATOR_ID91 0x91 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __LINUX_REGULATOR_MT6397_H */ 42