1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Chenglin Xu <chenglin.xu@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LINUX_REGULATOR_mt6380_H 8*4882a593Smuzhiyun #define __LINUX_REGULATOR_mt6380_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun enum { 11*4882a593Smuzhiyun MT6380_ID_VCPU = 0, 12*4882a593Smuzhiyun MT6380_ID_VCORE, 13*4882a593Smuzhiyun MT6380_ID_VRF, 14*4882a593Smuzhiyun MT6380_ID_VMLDO, 15*4882a593Smuzhiyun MT6380_ID_VALDO, 16*4882a593Smuzhiyun MT6380_ID_VPHYLDO, 17*4882a593Smuzhiyun MT6380_ID_VDDRLDO, 18*4882a593Smuzhiyun MT6380_ID_VTLDO, 19*4882a593Smuzhiyun MT6380_ID_RG_MAX, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MT6380_MAX_REGULATOR MT6380_ID_RG_MAX 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif /* __LINUX_REGULATOR_mt6380_H */ 25