xref: /OK3568_Linux_fs/kernel/include/linux/regulator/max8952.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * max8952.h - Voltage regulation for the Maxim 8952
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 2010 Samsung Electrnoics
6*4882a593Smuzhiyun  *  MyungJoo Ham <myungjoo.ham@samsung.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef REGULATOR_MAX8952
10*4882a593Smuzhiyun #define REGULATOR_MAX8952
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/regulator/machine.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun enum {
15*4882a593Smuzhiyun 	MAX8952_DVS_MODE0,
16*4882a593Smuzhiyun 	MAX8952_DVS_MODE1,
17*4882a593Smuzhiyun 	MAX8952_DVS_MODE2,
18*4882a593Smuzhiyun 	MAX8952_DVS_MODE3,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun enum {
22*4882a593Smuzhiyun 	MAX8952_DVS_770mV = 0,
23*4882a593Smuzhiyun 	MAX8952_DVS_780mV,
24*4882a593Smuzhiyun 	MAX8952_DVS_790mV,
25*4882a593Smuzhiyun 	MAX8952_DVS_800mV,
26*4882a593Smuzhiyun 	MAX8952_DVS_810mV,
27*4882a593Smuzhiyun 	MAX8952_DVS_820mV,
28*4882a593Smuzhiyun 	MAX8952_DVS_830mV,
29*4882a593Smuzhiyun 	MAX8952_DVS_840mV,
30*4882a593Smuzhiyun 	MAX8952_DVS_850mV,
31*4882a593Smuzhiyun 	MAX8952_DVS_860mV,
32*4882a593Smuzhiyun 	MAX8952_DVS_870mV,
33*4882a593Smuzhiyun 	MAX8952_DVS_880mV,
34*4882a593Smuzhiyun 	MAX8952_DVS_890mV,
35*4882a593Smuzhiyun 	MAX8952_DVS_900mV,
36*4882a593Smuzhiyun 	MAX8952_DVS_910mV,
37*4882a593Smuzhiyun 	MAX8952_DVS_920mV,
38*4882a593Smuzhiyun 	MAX8952_DVS_930mV,
39*4882a593Smuzhiyun 	MAX8952_DVS_940mV,
40*4882a593Smuzhiyun 	MAX8952_DVS_950mV,
41*4882a593Smuzhiyun 	MAX8952_DVS_960mV,
42*4882a593Smuzhiyun 	MAX8952_DVS_970mV,
43*4882a593Smuzhiyun 	MAX8952_DVS_980mV,
44*4882a593Smuzhiyun 	MAX8952_DVS_990mV,
45*4882a593Smuzhiyun 	MAX8952_DVS_1000mV,
46*4882a593Smuzhiyun 	MAX8952_DVS_1010mV,
47*4882a593Smuzhiyun 	MAX8952_DVS_1020mV,
48*4882a593Smuzhiyun 	MAX8952_DVS_1030mV,
49*4882a593Smuzhiyun 	MAX8952_DVS_1040mV,
50*4882a593Smuzhiyun 	MAX8952_DVS_1050mV,
51*4882a593Smuzhiyun 	MAX8952_DVS_1060mV,
52*4882a593Smuzhiyun 	MAX8952_DVS_1070mV,
53*4882a593Smuzhiyun 	MAX8952_DVS_1080mV,
54*4882a593Smuzhiyun 	MAX8952_DVS_1090mV,
55*4882a593Smuzhiyun 	MAX8952_DVS_1100mV,
56*4882a593Smuzhiyun 	MAX8952_DVS_1110mV,
57*4882a593Smuzhiyun 	MAX8952_DVS_1120mV,
58*4882a593Smuzhiyun 	MAX8952_DVS_1130mV,
59*4882a593Smuzhiyun 	MAX8952_DVS_1140mV,
60*4882a593Smuzhiyun 	MAX8952_DVS_1150mV,
61*4882a593Smuzhiyun 	MAX8952_DVS_1160mV,
62*4882a593Smuzhiyun 	MAX8952_DVS_1170mV,
63*4882a593Smuzhiyun 	MAX8952_DVS_1180mV,
64*4882a593Smuzhiyun 	MAX8952_DVS_1190mV,
65*4882a593Smuzhiyun 	MAX8952_DVS_1200mV,
66*4882a593Smuzhiyun 	MAX8952_DVS_1210mV,
67*4882a593Smuzhiyun 	MAX8952_DVS_1220mV,
68*4882a593Smuzhiyun 	MAX8952_DVS_1230mV,
69*4882a593Smuzhiyun 	MAX8952_DVS_1240mV,
70*4882a593Smuzhiyun 	MAX8952_DVS_1250mV,
71*4882a593Smuzhiyun 	MAX8952_DVS_1260mV,
72*4882a593Smuzhiyun 	MAX8952_DVS_1270mV,
73*4882a593Smuzhiyun 	MAX8952_DVS_1280mV,
74*4882a593Smuzhiyun 	MAX8952_DVS_1290mV,
75*4882a593Smuzhiyun 	MAX8952_DVS_1300mV,
76*4882a593Smuzhiyun 	MAX8952_DVS_1310mV,
77*4882a593Smuzhiyun 	MAX8952_DVS_1320mV,
78*4882a593Smuzhiyun 	MAX8952_DVS_1330mV,
79*4882a593Smuzhiyun 	MAX8952_DVS_1340mV,
80*4882a593Smuzhiyun 	MAX8952_DVS_1350mV,
81*4882a593Smuzhiyun 	MAX8952_DVS_1360mV,
82*4882a593Smuzhiyun 	MAX8952_DVS_1370mV,
83*4882a593Smuzhiyun 	MAX8952_DVS_1380mV,
84*4882a593Smuzhiyun 	MAX8952_DVS_1390mV,
85*4882a593Smuzhiyun 	MAX8952_DVS_1400mV,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun enum {
89*4882a593Smuzhiyun 	MAX8952_SYNC_FREQ_26MHZ, /* Default */
90*4882a593Smuzhiyun 	MAX8952_SYNC_FREQ_13MHZ,
91*4882a593Smuzhiyun 	MAX8952_SYNC_FREQ_19_2MHZ,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun enum {
95*4882a593Smuzhiyun 	MAX8952_RAMP_32mV_us = 0, /* Default */
96*4882a593Smuzhiyun 	MAX8952_RAMP_16mV_us,
97*4882a593Smuzhiyun 	MAX8952_RAMP_8mV_us,
98*4882a593Smuzhiyun 	MAX8952_RAMP_4mV_us,
99*4882a593Smuzhiyun 	MAX8952_RAMP_2mV_us,
100*4882a593Smuzhiyun 	MAX8952_RAMP_1mV_us,
101*4882a593Smuzhiyun 	MAX8952_RAMP_0_5mV_us,
102*4882a593Smuzhiyun 	MAX8952_RAMP_0_25mV_us,
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun #define MAX8952_NUM_DVS_MODE	4
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun struct max8952_platform_data {
108*4882a593Smuzhiyun 	u32 default_mode;
109*4882a593Smuzhiyun 	u32 dvs_mode[MAX8952_NUM_DVS_MODE]; /* MAX8952_DVS_MODEx_XXXXmV */
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	u32 sync_freq;
112*4882a593Smuzhiyun 	u32 ramp_speed;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	struct regulator_init_data *reg_data;
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #endif /* REGULATOR_MAX8952 */
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