1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Interface of Maxim max8649 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009-2010 Marvell International Ltd. 6*4882a593Smuzhiyun * Haojian Zhuang <haojian.zhuang@marvell.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __LINUX_REGULATOR_MAX8649_H 10*4882a593Smuzhiyun #define __LINUX_REGULATOR_MAX8649_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/regulator/machine.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun enum { 15*4882a593Smuzhiyun MAX8649_EXTCLK_26MHZ = 0, 16*4882a593Smuzhiyun MAX8649_EXTCLK_13MHZ, 17*4882a593Smuzhiyun MAX8649_EXTCLK_19MHZ, /* 19.2MHz */ 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum { 21*4882a593Smuzhiyun MAX8649_RAMP_32MV = 0, 22*4882a593Smuzhiyun MAX8649_RAMP_16MV, 23*4882a593Smuzhiyun MAX8649_RAMP_8MV, 24*4882a593Smuzhiyun MAX8649_RAMP_4MV, 25*4882a593Smuzhiyun MAX8649_RAMP_2MV, 26*4882a593Smuzhiyun MAX8649_RAMP_1MV, 27*4882a593Smuzhiyun MAX8649_RAMP_0_5MV, 28*4882a593Smuzhiyun MAX8649_RAMP_0_25MV, 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct max8649_platform_data { 32*4882a593Smuzhiyun struct regulator_init_data *regulator; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun unsigned mode:2; /* bit[1:0] = VID1,VID0 */ 35*4882a593Smuzhiyun unsigned extclk_freq:2; 36*4882a593Smuzhiyun unsigned extclk:1; 37*4882a593Smuzhiyun unsigned ramp_timing:3; 38*4882a593Smuzhiyun unsigned ramp_down:1; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __LINUX_REGULATOR_MAX8649_H */ 42