xref: /OK3568_Linux_fs/kernel/include/linux/regulator/ab8500.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) ST-Ericsson SA 2010
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
6*4882a593Smuzhiyun  *          Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
7*4882a593Smuzhiyun  *          Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #ifndef __LINUX_MFD_AB8500_REGULATOR_H
11*4882a593Smuzhiyun #define __LINUX_MFD_AB8500_REGULATOR_H
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /* AB8500 regulators */
16*4882a593Smuzhiyun enum ab8500_regulator_id {
17*4882a593Smuzhiyun 	AB8500_LDO_AUX1,
18*4882a593Smuzhiyun 	AB8500_LDO_AUX2,
19*4882a593Smuzhiyun 	AB8500_LDO_AUX3,
20*4882a593Smuzhiyun 	AB8500_LDO_INTCORE,
21*4882a593Smuzhiyun 	AB8500_LDO_TVOUT,
22*4882a593Smuzhiyun 	AB8500_LDO_AUDIO,
23*4882a593Smuzhiyun 	AB8500_LDO_ANAMIC1,
24*4882a593Smuzhiyun 	AB8500_LDO_ANAMIC2,
25*4882a593Smuzhiyun 	AB8500_LDO_DMIC,
26*4882a593Smuzhiyun 	AB8500_LDO_ANA,
27*4882a593Smuzhiyun 	AB8500_NUM_REGULATORS,
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* AB8505 regulators */
31*4882a593Smuzhiyun enum ab8505_regulator_id {
32*4882a593Smuzhiyun 	AB8505_LDO_AUX1,
33*4882a593Smuzhiyun 	AB8505_LDO_AUX2,
34*4882a593Smuzhiyun 	AB8505_LDO_AUX3,
35*4882a593Smuzhiyun 	AB8505_LDO_AUX4,
36*4882a593Smuzhiyun 	AB8505_LDO_AUX5,
37*4882a593Smuzhiyun 	AB8505_LDO_AUX6,
38*4882a593Smuzhiyun 	AB8505_LDO_INTCORE,
39*4882a593Smuzhiyun 	AB8505_LDO_ADC,
40*4882a593Smuzhiyun 	AB8505_LDO_AUDIO,
41*4882a593Smuzhiyun 	AB8505_LDO_ANAMIC1,
42*4882a593Smuzhiyun 	AB8505_LDO_ANAMIC2,
43*4882a593Smuzhiyun 	AB8505_LDO_AUX8,
44*4882a593Smuzhiyun 	AB8505_LDO_ANA,
45*4882a593Smuzhiyun 	AB8505_NUM_REGULATORS,
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* AB8500 and AB8505 register initialization */
49*4882a593Smuzhiyun struct ab8500_regulator_reg_init {
50*4882a593Smuzhiyun 	int id;
51*4882a593Smuzhiyun 	u8 mask;
52*4882a593Smuzhiyun 	u8 value;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define INIT_REGULATOR_REGISTER(_id, _mask, _value)	\
56*4882a593Smuzhiyun 	{						\
57*4882a593Smuzhiyun 		.id = _id,				\
58*4882a593Smuzhiyun 		.mask = _mask,				\
59*4882a593Smuzhiyun 		.value = _value,			\
60*4882a593Smuzhiyun 	}
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* AB8500 registers */
63*4882a593Smuzhiyun enum ab8500_regulator_reg {
64*4882a593Smuzhiyun 	AB8500_REGUREQUESTCTRL2,
65*4882a593Smuzhiyun 	AB8500_REGUREQUESTCTRL3,
66*4882a593Smuzhiyun 	AB8500_REGUREQUESTCTRL4,
67*4882a593Smuzhiyun 	AB8500_REGUSYSCLKREQ1HPVALID1,
68*4882a593Smuzhiyun 	AB8500_REGUSYSCLKREQ1HPVALID2,
69*4882a593Smuzhiyun 	AB8500_REGUHWHPREQ1VALID1,
70*4882a593Smuzhiyun 	AB8500_REGUHWHPREQ1VALID2,
71*4882a593Smuzhiyun 	AB8500_REGUHWHPREQ2VALID1,
72*4882a593Smuzhiyun 	AB8500_REGUHWHPREQ2VALID2,
73*4882a593Smuzhiyun 	AB8500_REGUSWHPREQVALID1,
74*4882a593Smuzhiyun 	AB8500_REGUSWHPREQVALID2,
75*4882a593Smuzhiyun 	AB8500_REGUSYSCLKREQVALID1,
76*4882a593Smuzhiyun 	AB8500_REGUSYSCLKREQVALID2,
77*4882a593Smuzhiyun 	AB8500_REGUMISC1,
78*4882a593Smuzhiyun 	AB8500_VAUDIOSUPPLY,
79*4882a593Smuzhiyun 	AB8500_REGUCTRL1VAMIC,
80*4882a593Smuzhiyun 	AB8500_VPLLVANAREGU,
81*4882a593Smuzhiyun 	AB8500_VREFDDR,
82*4882a593Smuzhiyun 	AB8500_EXTSUPPLYREGU,
83*4882a593Smuzhiyun 	AB8500_VAUX12REGU,
84*4882a593Smuzhiyun 	AB8500_VRF1VAUX3REGU,
85*4882a593Smuzhiyun 	AB8500_VAUX1SEL,
86*4882a593Smuzhiyun 	AB8500_VAUX2SEL,
87*4882a593Smuzhiyun 	AB8500_VRF1VAUX3SEL,
88*4882a593Smuzhiyun 	AB8500_REGUCTRL2SPARE,
89*4882a593Smuzhiyun 	AB8500_REGUCTRLDISCH,
90*4882a593Smuzhiyun 	AB8500_REGUCTRLDISCH2,
91*4882a593Smuzhiyun 	AB8500_NUM_REGULATOR_REGISTERS,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /* AB8505 registers */
95*4882a593Smuzhiyun enum ab8505_regulator_reg {
96*4882a593Smuzhiyun 	AB8505_REGUREQUESTCTRL1,
97*4882a593Smuzhiyun 	AB8505_REGUREQUESTCTRL2,
98*4882a593Smuzhiyun 	AB8505_REGUREQUESTCTRL3,
99*4882a593Smuzhiyun 	AB8505_REGUREQUESTCTRL4,
100*4882a593Smuzhiyun 	AB8505_REGUSYSCLKREQ1HPVALID1,
101*4882a593Smuzhiyun 	AB8505_REGUSYSCLKREQ1HPVALID2,
102*4882a593Smuzhiyun 	AB8505_REGUHWHPREQ1VALID1,
103*4882a593Smuzhiyun 	AB8505_REGUHWHPREQ1VALID2,
104*4882a593Smuzhiyun 	AB8505_REGUHWHPREQ2VALID1,
105*4882a593Smuzhiyun 	AB8505_REGUHWHPREQ2VALID2,
106*4882a593Smuzhiyun 	AB8505_REGUSWHPREQVALID1,
107*4882a593Smuzhiyun 	AB8505_REGUSWHPREQVALID2,
108*4882a593Smuzhiyun 	AB8505_REGUSYSCLKREQVALID1,
109*4882a593Smuzhiyun 	AB8505_REGUSYSCLKREQVALID2,
110*4882a593Smuzhiyun 	AB8505_REGUVAUX4REQVALID,
111*4882a593Smuzhiyun 	AB8505_REGUMISC1,
112*4882a593Smuzhiyun 	AB8505_VAUDIOSUPPLY,
113*4882a593Smuzhiyun 	AB8505_REGUCTRL1VAMIC,
114*4882a593Smuzhiyun 	AB8505_VSMPSAREGU,
115*4882a593Smuzhiyun 	AB8505_VSMPSBREGU,
116*4882a593Smuzhiyun 	AB8505_VSAFEREGU, /* NOTE! PRCMU register */
117*4882a593Smuzhiyun 	AB8505_VPLLVANAREGU,
118*4882a593Smuzhiyun 	AB8505_EXTSUPPLYREGU,
119*4882a593Smuzhiyun 	AB8505_VAUX12REGU,
120*4882a593Smuzhiyun 	AB8505_VRF1VAUX3REGU,
121*4882a593Smuzhiyun 	AB8505_VSMPSASEL1,
122*4882a593Smuzhiyun 	AB8505_VSMPSASEL2,
123*4882a593Smuzhiyun 	AB8505_VSMPSASEL3,
124*4882a593Smuzhiyun 	AB8505_VSMPSBSEL1,
125*4882a593Smuzhiyun 	AB8505_VSMPSBSEL2,
126*4882a593Smuzhiyun 	AB8505_VSMPSBSEL3,
127*4882a593Smuzhiyun 	AB8505_VSAFESEL1, /* NOTE! PRCMU register */
128*4882a593Smuzhiyun 	AB8505_VSAFESEL2, /* NOTE! PRCMU register */
129*4882a593Smuzhiyun 	AB8505_VSAFESEL3, /* NOTE! PRCMU register */
130*4882a593Smuzhiyun 	AB8505_VAUX1SEL,
131*4882a593Smuzhiyun 	AB8505_VAUX2SEL,
132*4882a593Smuzhiyun 	AB8505_VRF1VAUX3SEL,
133*4882a593Smuzhiyun 	AB8505_VAUX4REQCTRL,
134*4882a593Smuzhiyun 	AB8505_VAUX4REGU,
135*4882a593Smuzhiyun 	AB8505_VAUX4SEL,
136*4882a593Smuzhiyun 	AB8505_REGUCTRLDISCH,
137*4882a593Smuzhiyun 	AB8505_REGUCTRLDISCH2,
138*4882a593Smuzhiyun 	AB8505_REGUCTRLDISCH3,
139*4882a593Smuzhiyun 	AB8505_CTRLVAUX5,
140*4882a593Smuzhiyun 	AB8505_CTRLVAUX6,
141*4882a593Smuzhiyun 	AB8505_NUM_REGULATOR_REGISTERS,
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun /* AB8500 external regulators */
145*4882a593Smuzhiyun struct ab8500_ext_regulator_cfg {
146*4882a593Smuzhiyun 	bool hwreq; /* requires hw mode or high power mode */
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun enum ab8500_ext_regulator_id {
150*4882a593Smuzhiyun 	AB8500_EXT_SUPPLY1,
151*4882a593Smuzhiyun 	AB8500_EXT_SUPPLY2,
152*4882a593Smuzhiyun 	AB8500_EXT_SUPPLY3,
153*4882a593Smuzhiyun 	AB8500_NUM_EXT_REGULATORS,
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun /* AB8500 regulator platform data */
157*4882a593Smuzhiyun struct ab8500_regulator_platform_data {
158*4882a593Smuzhiyun 	int num_reg_init;
159*4882a593Smuzhiyun 	struct ab8500_regulator_reg_init *reg_init;
160*4882a593Smuzhiyun 	int num_regulator;
161*4882a593Smuzhiyun 	struct regulator_init_data *regulator;
162*4882a593Smuzhiyun 	int num_ext_regulator;
163*4882a593Smuzhiyun 	struct regulator_init_data *ext_regulator;
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #endif
167