1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun #ifndef __LINUX_REGMAP_H
3*4882a593Smuzhiyun #define __LINUX_REGMAP_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /*
6*4882a593Smuzhiyun * Register map access API
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright 2011 Wolfson Microelectronics plc
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/list.h>
14*4882a593Smuzhiyun #include <linux/rbtree.h>
15*4882a593Smuzhiyun #include <linux/ktime.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/err.h>
18*4882a593Smuzhiyun #include <linux/bug.h>
19*4882a593Smuzhiyun #include <linux/lockdep.h>
20*4882a593Smuzhiyun #include <linux/iopoll.h>
21*4882a593Smuzhiyun #include <linux/fwnode.h>
22*4882a593Smuzhiyun #include <linux/android_kabi.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct module;
25*4882a593Smuzhiyun struct clk;
26*4882a593Smuzhiyun struct device;
27*4882a593Smuzhiyun struct device_node;
28*4882a593Smuzhiyun struct i2c_client;
29*4882a593Smuzhiyun struct i3c_device;
30*4882a593Smuzhiyun struct irq_domain;
31*4882a593Smuzhiyun struct slim_device;
32*4882a593Smuzhiyun struct spi_device;
33*4882a593Smuzhiyun struct spmi_device;
34*4882a593Smuzhiyun struct regmap;
35*4882a593Smuzhiyun struct regmap_range_cfg;
36*4882a593Smuzhiyun struct regmap_field;
37*4882a593Smuzhiyun struct snd_ac97;
38*4882a593Smuzhiyun struct sdw_slave;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* An enum of all the supported cache types */
41*4882a593Smuzhiyun enum regcache_type {
42*4882a593Smuzhiyun REGCACHE_NONE,
43*4882a593Smuzhiyun REGCACHE_RBTREE,
44*4882a593Smuzhiyun REGCACHE_COMPRESSED,
45*4882a593Smuzhiyun REGCACHE_FLAT,
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /**
49*4882a593Smuzhiyun * struct reg_default - Default value for a register.
50*4882a593Smuzhiyun *
51*4882a593Smuzhiyun * @reg: Register address.
52*4882a593Smuzhiyun * @def: Register default value.
53*4882a593Smuzhiyun *
54*4882a593Smuzhiyun * We use an array of structs rather than a simple array as many modern devices
55*4882a593Smuzhiyun * have very sparse register maps.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun struct reg_default {
58*4882a593Smuzhiyun unsigned int reg;
59*4882a593Smuzhiyun unsigned int def;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /**
63*4882a593Smuzhiyun * struct reg_sequence - An individual write from a sequence of writes.
64*4882a593Smuzhiyun *
65*4882a593Smuzhiyun * @reg: Register address.
66*4882a593Smuzhiyun * @def: Register value.
67*4882a593Smuzhiyun * @delay_us: Delay to be applied after the register write in microseconds
68*4882a593Smuzhiyun *
69*4882a593Smuzhiyun * Register/value pairs for sequences of writes with an optional delay in
70*4882a593Smuzhiyun * microseconds to be applied after each write.
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun struct reg_sequence {
73*4882a593Smuzhiyun unsigned int reg;
74*4882a593Smuzhiyun unsigned int def;
75*4882a593Smuzhiyun unsigned int delay_us;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define REG_SEQ(_reg, _def, _delay_us) { \
79*4882a593Smuzhiyun .reg = _reg, \
80*4882a593Smuzhiyun .def = _def, \
81*4882a593Smuzhiyun .delay_us = _delay_us, \
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun #define REG_SEQ0(_reg, _def) REG_SEQ(_reg, _def, 0)
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /**
86*4882a593Smuzhiyun * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs
87*4882a593Smuzhiyun *
88*4882a593Smuzhiyun * @map: Regmap to read from
89*4882a593Smuzhiyun * @addr: Address to poll
90*4882a593Smuzhiyun * @val: Unsigned integer variable to read the value into
91*4882a593Smuzhiyun * @cond: Break condition (usually involving @val)
92*4882a593Smuzhiyun * @sleep_us: Maximum time to sleep between reads in us (0
93*4882a593Smuzhiyun * tight-loops). Should be less than ~20ms since usleep_range
94*4882a593Smuzhiyun * is used (see Documentation/timers/timers-howto.rst).
95*4882a593Smuzhiyun * @timeout_us: Timeout in us, 0 means never timeout
96*4882a593Smuzhiyun *
97*4882a593Smuzhiyun * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
98*4882a593Smuzhiyun * error return value in case of a error read. In the two former cases,
99*4882a593Smuzhiyun * the last read value at @addr is stored in @val. Must not be called
100*4882a593Smuzhiyun * from atomic context if sleep_us or timeout_us are used.
101*4882a593Smuzhiyun *
102*4882a593Smuzhiyun * This is modelled after the readx_poll_timeout macros in linux/iopoll.h.
103*4882a593Smuzhiyun */
104*4882a593Smuzhiyun #define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_us) \
105*4882a593Smuzhiyun ({ \
106*4882a593Smuzhiyun int __ret, __tmp; \
107*4882a593Smuzhiyun __tmp = read_poll_timeout(regmap_read, __ret, __ret || (cond), \
108*4882a593Smuzhiyun sleep_us, timeout_us, false, (map), (addr), &(val)); \
109*4882a593Smuzhiyun __ret ?: __tmp; \
110*4882a593Smuzhiyun })
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /**
113*4882a593Smuzhiyun * regmap_read_poll_timeout_atomic - Poll until a condition is met or a timeout occurs
114*4882a593Smuzhiyun *
115*4882a593Smuzhiyun * @map: Regmap to read from
116*4882a593Smuzhiyun * @addr: Address to poll
117*4882a593Smuzhiyun * @val: Unsigned integer variable to read the value into
118*4882a593Smuzhiyun * @cond: Break condition (usually involving @val)
119*4882a593Smuzhiyun * @delay_us: Time to udelay between reads in us (0 tight-loops).
120*4882a593Smuzhiyun * Should be less than ~10us since udelay is used
121*4882a593Smuzhiyun * (see Documentation/timers/timers-howto.rst).
122*4882a593Smuzhiyun * @timeout_us: Timeout in us, 0 means never timeout
123*4882a593Smuzhiyun *
124*4882a593Smuzhiyun * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
125*4882a593Smuzhiyun * error return value in case of a error read. In the two former cases,
126*4882a593Smuzhiyun * the last read value at @addr is stored in @val.
127*4882a593Smuzhiyun *
128*4882a593Smuzhiyun * This is modelled after the readx_poll_timeout_atomic macros in linux/iopoll.h.
129*4882a593Smuzhiyun *
130*4882a593Smuzhiyun * Note: In general regmap cannot be used in atomic context. If you want to use
131*4882a593Smuzhiyun * this macro then first setup your regmap for atomic use (flat or no cache
132*4882a593Smuzhiyun * and MMIO regmap).
133*4882a593Smuzhiyun */
134*4882a593Smuzhiyun #define regmap_read_poll_timeout_atomic(map, addr, val, cond, delay_us, timeout_us) \
135*4882a593Smuzhiyun ({ \
136*4882a593Smuzhiyun u64 __timeout_us = (timeout_us); \
137*4882a593Smuzhiyun unsigned long __delay_us = (delay_us); \
138*4882a593Smuzhiyun ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
139*4882a593Smuzhiyun int __ret; \
140*4882a593Smuzhiyun for (;;) { \
141*4882a593Smuzhiyun __ret = regmap_read((map), (addr), &(val)); \
142*4882a593Smuzhiyun if (__ret) \
143*4882a593Smuzhiyun break; \
144*4882a593Smuzhiyun if (cond) \
145*4882a593Smuzhiyun break; \
146*4882a593Smuzhiyun if ((__timeout_us) && \
147*4882a593Smuzhiyun ktime_compare(ktime_get(), __timeout) > 0) { \
148*4882a593Smuzhiyun __ret = regmap_read((map), (addr), &(val)); \
149*4882a593Smuzhiyun break; \
150*4882a593Smuzhiyun } \
151*4882a593Smuzhiyun if (__delay_us) \
152*4882a593Smuzhiyun udelay(__delay_us); \
153*4882a593Smuzhiyun } \
154*4882a593Smuzhiyun __ret ?: ((cond) ? 0 : -ETIMEDOUT); \
155*4882a593Smuzhiyun })
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /**
158*4882a593Smuzhiyun * regmap_field_read_poll_timeout - Poll until a condition is met or timeout
159*4882a593Smuzhiyun *
160*4882a593Smuzhiyun * @field: Regmap field to read from
161*4882a593Smuzhiyun * @val: Unsigned integer variable to read the value into
162*4882a593Smuzhiyun * @cond: Break condition (usually involving @val)
163*4882a593Smuzhiyun * @sleep_us: Maximum time to sleep between reads in us (0
164*4882a593Smuzhiyun * tight-loops). Should be less than ~20ms since usleep_range
165*4882a593Smuzhiyun * is used (see Documentation/timers/timers-howto.rst).
166*4882a593Smuzhiyun * @timeout_us: Timeout in us, 0 means never timeout
167*4882a593Smuzhiyun *
168*4882a593Smuzhiyun * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_field_read
169*4882a593Smuzhiyun * error return value in case of a error read. In the two former cases,
170*4882a593Smuzhiyun * the last read value at @addr is stored in @val. Must not be called
171*4882a593Smuzhiyun * from atomic context if sleep_us or timeout_us are used.
172*4882a593Smuzhiyun *
173*4882a593Smuzhiyun * This is modelled after the readx_poll_timeout macros in linux/iopoll.h.
174*4882a593Smuzhiyun */
175*4882a593Smuzhiyun #define regmap_field_read_poll_timeout(field, val, cond, sleep_us, timeout_us) \
176*4882a593Smuzhiyun ({ \
177*4882a593Smuzhiyun int __ret, __tmp; \
178*4882a593Smuzhiyun __tmp = read_poll_timeout(regmap_field_read, __ret, __ret || (cond), \
179*4882a593Smuzhiyun sleep_us, timeout_us, false, (field), &(val)); \
180*4882a593Smuzhiyun __ret ?: __tmp; \
181*4882a593Smuzhiyun })
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun #ifdef CONFIG_REGMAP
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun enum regmap_endian {
186*4882a593Smuzhiyun /* Unspecified -> 0 -> Backwards compatible default */
187*4882a593Smuzhiyun REGMAP_ENDIAN_DEFAULT = 0,
188*4882a593Smuzhiyun REGMAP_ENDIAN_BIG,
189*4882a593Smuzhiyun REGMAP_ENDIAN_LITTLE,
190*4882a593Smuzhiyun REGMAP_ENDIAN_NATIVE,
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /**
194*4882a593Smuzhiyun * struct regmap_range - A register range, used for access related checks
195*4882a593Smuzhiyun * (readable/writeable/volatile/precious checks)
196*4882a593Smuzhiyun *
197*4882a593Smuzhiyun * @range_min: address of first register
198*4882a593Smuzhiyun * @range_max: address of last register
199*4882a593Smuzhiyun */
200*4882a593Smuzhiyun struct regmap_range {
201*4882a593Smuzhiyun unsigned int range_min;
202*4882a593Smuzhiyun unsigned int range_max;
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun #define regmap_reg_range(low, high) { .range_min = low, .range_max = high, }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /**
208*4882a593Smuzhiyun * struct regmap_access_table - A table of register ranges for access checks
209*4882a593Smuzhiyun *
210*4882a593Smuzhiyun * @yes_ranges : pointer to an array of regmap ranges used as "yes ranges"
211*4882a593Smuzhiyun * @n_yes_ranges: size of the above array
212*4882a593Smuzhiyun * @no_ranges: pointer to an array of regmap ranges used as "no ranges"
213*4882a593Smuzhiyun * @n_no_ranges: size of the above array
214*4882a593Smuzhiyun *
215*4882a593Smuzhiyun * A table of ranges including some yes ranges and some no ranges.
216*4882a593Smuzhiyun * If a register belongs to a no_range, the corresponding check function
217*4882a593Smuzhiyun * will return false. If a register belongs to a yes range, the corresponding
218*4882a593Smuzhiyun * check function will return true. "no_ranges" are searched first.
219*4882a593Smuzhiyun */
220*4882a593Smuzhiyun struct regmap_access_table {
221*4882a593Smuzhiyun const struct regmap_range *yes_ranges;
222*4882a593Smuzhiyun unsigned int n_yes_ranges;
223*4882a593Smuzhiyun const struct regmap_range *no_ranges;
224*4882a593Smuzhiyun unsigned int n_no_ranges;
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun typedef void (*regmap_lock)(void *);
228*4882a593Smuzhiyun typedef void (*regmap_unlock)(void *);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /**
231*4882a593Smuzhiyun * struct regmap_config - Configuration for the register map of a device.
232*4882a593Smuzhiyun *
233*4882a593Smuzhiyun * @name: Optional name of the regmap. Useful when a device has multiple
234*4882a593Smuzhiyun * register regions.
235*4882a593Smuzhiyun *
236*4882a593Smuzhiyun * @reg_bits: Number of bits in a register address, mandatory.
237*4882a593Smuzhiyun * @reg_stride: The register address stride. Valid register addresses are a
238*4882a593Smuzhiyun * multiple of this value. If set to 0, a value of 1 will be
239*4882a593Smuzhiyun * used.
240*4882a593Smuzhiyun * @pad_bits: Number of bits of padding between register and value.
241*4882a593Smuzhiyun * @val_bits: Number of bits in a register value, mandatory.
242*4882a593Smuzhiyun *
243*4882a593Smuzhiyun * @writeable_reg: Optional callback returning true if the register
244*4882a593Smuzhiyun * can be written to. If this field is NULL but wr_table
245*4882a593Smuzhiyun * (see below) is not, the check is performed on such table
246*4882a593Smuzhiyun * (a register is writeable if it belongs to one of the ranges
247*4882a593Smuzhiyun * specified by wr_table).
248*4882a593Smuzhiyun * @readable_reg: Optional callback returning true if the register
249*4882a593Smuzhiyun * can be read from. If this field is NULL but rd_table
250*4882a593Smuzhiyun * (see below) is not, the check is performed on such table
251*4882a593Smuzhiyun * (a register is readable if it belongs to one of the ranges
252*4882a593Smuzhiyun * specified by rd_table).
253*4882a593Smuzhiyun * @volatile_reg: Optional callback returning true if the register
254*4882a593Smuzhiyun * value can't be cached. If this field is NULL but
255*4882a593Smuzhiyun * volatile_table (see below) is not, the check is performed on
256*4882a593Smuzhiyun * such table (a register is volatile if it belongs to one of
257*4882a593Smuzhiyun * the ranges specified by volatile_table).
258*4882a593Smuzhiyun * @precious_reg: Optional callback returning true if the register
259*4882a593Smuzhiyun * should not be read outside of a call from the driver
260*4882a593Smuzhiyun * (e.g., a clear on read interrupt status register). If this
261*4882a593Smuzhiyun * field is NULL but precious_table (see below) is not, the
262*4882a593Smuzhiyun * check is performed on such table (a register is precious if
263*4882a593Smuzhiyun * it belongs to one of the ranges specified by precious_table).
264*4882a593Smuzhiyun * @writeable_noinc_reg: Optional callback returning true if the register
265*4882a593Smuzhiyun * supports multiple write operations without incrementing
266*4882a593Smuzhiyun * the register number. If this field is NULL but
267*4882a593Smuzhiyun * wr_noinc_table (see below) is not, the check is
268*4882a593Smuzhiyun * performed on such table (a register is no increment
269*4882a593Smuzhiyun * writeable if it belongs to one of the ranges specified
270*4882a593Smuzhiyun * by wr_noinc_table).
271*4882a593Smuzhiyun * @readable_noinc_reg: Optional callback returning true if the register
272*4882a593Smuzhiyun * supports multiple read operations without incrementing
273*4882a593Smuzhiyun * the register number. If this field is NULL but
274*4882a593Smuzhiyun * rd_noinc_table (see below) is not, the check is
275*4882a593Smuzhiyun * performed on such table (a register is no increment
276*4882a593Smuzhiyun * readable if it belongs to one of the ranges specified
277*4882a593Smuzhiyun * by rd_noinc_table).
278*4882a593Smuzhiyun * @disable_locking: This regmap is either protected by external means or
279*4882a593Smuzhiyun * is guaranteed not to be accessed from multiple threads.
280*4882a593Smuzhiyun * Don't use any locking mechanisms.
281*4882a593Smuzhiyun * @lock: Optional lock callback (overrides regmap's default lock
282*4882a593Smuzhiyun * function, based on spinlock or mutex).
283*4882a593Smuzhiyun * @unlock: As above for unlocking.
284*4882a593Smuzhiyun * @lock_arg: this field is passed as the only argument of lock/unlock
285*4882a593Smuzhiyun * functions (ignored in case regular lock/unlock functions
286*4882a593Smuzhiyun * are not overridden).
287*4882a593Smuzhiyun * @reg_read: Optional callback that if filled will be used to perform
288*4882a593Smuzhiyun * all the reads from the registers. Should only be provided for
289*4882a593Smuzhiyun * devices whose read operation cannot be represented as a simple
290*4882a593Smuzhiyun * read operation on a bus such as SPI, I2C, etc. Most of the
291*4882a593Smuzhiyun * devices do not need this.
292*4882a593Smuzhiyun * @reg_write: Same as above for writing.
293*4882a593Smuzhiyun * @fast_io: Register IO is fast. Use a spinlock instead of a mutex
294*4882a593Smuzhiyun * to perform locking. This field is ignored if custom lock/unlock
295*4882a593Smuzhiyun * functions are used (see fields lock/unlock of struct regmap_config).
296*4882a593Smuzhiyun * This field is a duplicate of a similar file in
297*4882a593Smuzhiyun * 'struct regmap_bus' and serves exact same purpose.
298*4882a593Smuzhiyun * Use it only for "no-bus" cases.
299*4882a593Smuzhiyun * @max_register: Optional, specifies the maximum valid register address.
300*4882a593Smuzhiyun * @wr_table: Optional, points to a struct regmap_access_table specifying
301*4882a593Smuzhiyun * valid ranges for write access.
302*4882a593Smuzhiyun * @rd_table: As above, for read access.
303*4882a593Smuzhiyun * @volatile_table: As above, for volatile registers.
304*4882a593Smuzhiyun * @precious_table: As above, for precious registers.
305*4882a593Smuzhiyun * @wr_noinc_table: As above, for no increment writeable registers.
306*4882a593Smuzhiyun * @rd_noinc_table: As above, for no increment readable registers.
307*4882a593Smuzhiyun * @reg_defaults: Power on reset values for registers (for use with
308*4882a593Smuzhiyun * register cache support).
309*4882a593Smuzhiyun * @num_reg_defaults: Number of elements in reg_defaults.
310*4882a593Smuzhiyun *
311*4882a593Smuzhiyun * @read_flag_mask: Mask to be set in the top bytes of the register when doing
312*4882a593Smuzhiyun * a read.
313*4882a593Smuzhiyun * @write_flag_mask: Mask to be set in the top bytes of the register when doing
314*4882a593Smuzhiyun * a write. If both read_flag_mask and write_flag_mask are
315*4882a593Smuzhiyun * empty and zero_flag_mask is not set the regmap_bus default
316*4882a593Smuzhiyun * masks are used.
317*4882a593Smuzhiyun * @zero_flag_mask: If set, read_flag_mask and write_flag_mask are used even
318*4882a593Smuzhiyun * if they are both empty.
319*4882a593Smuzhiyun * @use_single_read: If set, converts the bulk read operation into a series of
320*4882a593Smuzhiyun * single read operations. This is useful for a device that
321*4882a593Smuzhiyun * does not support bulk read.
322*4882a593Smuzhiyun * @use_single_write: If set, converts the bulk write operation into a series of
323*4882a593Smuzhiyun * single write operations. This is useful for a device that
324*4882a593Smuzhiyun * does not support bulk write.
325*4882a593Smuzhiyun * @can_multi_write: If set, the device supports the multi write mode of bulk
326*4882a593Smuzhiyun * write operations, if clear multi write requests will be
327*4882a593Smuzhiyun * split into individual write operations
328*4882a593Smuzhiyun *
329*4882a593Smuzhiyun * @cache_type: The actual cache type.
330*4882a593Smuzhiyun * @reg_defaults_raw: Power on reset values for registers (for use with
331*4882a593Smuzhiyun * register cache support).
332*4882a593Smuzhiyun * @num_reg_defaults_raw: Number of elements in reg_defaults_raw.
333*4882a593Smuzhiyun * @reg_format_endian: Endianness for formatted register addresses. If this is
334*4882a593Smuzhiyun * DEFAULT, the @reg_format_endian_default value from the
335*4882a593Smuzhiyun * regmap bus is used.
336*4882a593Smuzhiyun * @val_format_endian: Endianness for formatted register values. If this is
337*4882a593Smuzhiyun * DEFAULT, the @reg_format_endian_default value from the
338*4882a593Smuzhiyun * regmap bus is used.
339*4882a593Smuzhiyun *
340*4882a593Smuzhiyun * @ranges: Array of configuration entries for virtual address ranges.
341*4882a593Smuzhiyun * @num_ranges: Number of range configuration entries.
342*4882a593Smuzhiyun * @use_hwlock: Indicate if a hardware spinlock should be used.
343*4882a593Smuzhiyun * @hwlock_id: Specify the hardware spinlock id.
344*4882a593Smuzhiyun * @hwlock_mode: The hardware spinlock mode, should be HWLOCK_IRQSTATE,
345*4882a593Smuzhiyun * HWLOCK_IRQ or 0.
346*4882a593Smuzhiyun * @can_sleep: Optional, specifies whether regmap operations can sleep.
347*4882a593Smuzhiyun */
348*4882a593Smuzhiyun struct regmap_config {
349*4882a593Smuzhiyun const char *name;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun int reg_bits;
352*4882a593Smuzhiyun int reg_stride;
353*4882a593Smuzhiyun int pad_bits;
354*4882a593Smuzhiyun int val_bits;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun bool (*writeable_reg)(struct device *dev, unsigned int reg);
357*4882a593Smuzhiyun bool (*readable_reg)(struct device *dev, unsigned int reg);
358*4882a593Smuzhiyun bool (*volatile_reg)(struct device *dev, unsigned int reg);
359*4882a593Smuzhiyun bool (*precious_reg)(struct device *dev, unsigned int reg);
360*4882a593Smuzhiyun bool (*writeable_noinc_reg)(struct device *dev, unsigned int reg);
361*4882a593Smuzhiyun bool (*readable_noinc_reg)(struct device *dev, unsigned int reg);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun bool disable_locking;
364*4882a593Smuzhiyun regmap_lock lock;
365*4882a593Smuzhiyun regmap_unlock unlock;
366*4882a593Smuzhiyun void *lock_arg;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun int (*reg_read)(void *context, unsigned int reg, unsigned int *val);
369*4882a593Smuzhiyun int (*reg_write)(void *context, unsigned int reg, unsigned int val);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun bool fast_io;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun unsigned int max_register;
374*4882a593Smuzhiyun const struct regmap_access_table *wr_table;
375*4882a593Smuzhiyun const struct regmap_access_table *rd_table;
376*4882a593Smuzhiyun const struct regmap_access_table *volatile_table;
377*4882a593Smuzhiyun const struct regmap_access_table *precious_table;
378*4882a593Smuzhiyun const struct regmap_access_table *wr_noinc_table;
379*4882a593Smuzhiyun const struct regmap_access_table *rd_noinc_table;
380*4882a593Smuzhiyun const struct reg_default *reg_defaults;
381*4882a593Smuzhiyun unsigned int num_reg_defaults;
382*4882a593Smuzhiyun enum regcache_type cache_type;
383*4882a593Smuzhiyun const void *reg_defaults_raw;
384*4882a593Smuzhiyun unsigned int num_reg_defaults_raw;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun unsigned long read_flag_mask;
387*4882a593Smuzhiyun unsigned long write_flag_mask;
388*4882a593Smuzhiyun bool zero_flag_mask;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun bool use_single_read;
391*4882a593Smuzhiyun bool use_single_write;
392*4882a593Smuzhiyun bool can_multi_write;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun enum regmap_endian reg_format_endian;
395*4882a593Smuzhiyun enum regmap_endian val_format_endian;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun const struct regmap_range_cfg *ranges;
398*4882a593Smuzhiyun unsigned int num_ranges;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun bool use_hwlock;
401*4882a593Smuzhiyun unsigned int hwlock_id;
402*4882a593Smuzhiyun unsigned int hwlock_mode;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun bool can_sleep;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun ANDROID_KABI_RESERVE(1);
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /**
410*4882a593Smuzhiyun * struct regmap_range_cfg - Configuration for indirectly accessed or paged
411*4882a593Smuzhiyun * registers.
412*4882a593Smuzhiyun *
413*4882a593Smuzhiyun * @name: Descriptive name for diagnostics
414*4882a593Smuzhiyun *
415*4882a593Smuzhiyun * @range_min: Address of the lowest register address in virtual range.
416*4882a593Smuzhiyun * @range_max: Address of the highest register in virtual range.
417*4882a593Smuzhiyun *
418*4882a593Smuzhiyun * @selector_reg: Register with selector field.
419*4882a593Smuzhiyun * @selector_mask: Bit mask for selector value.
420*4882a593Smuzhiyun * @selector_shift: Bit shift for selector value.
421*4882a593Smuzhiyun *
422*4882a593Smuzhiyun * @window_start: Address of first (lowest) register in data window.
423*4882a593Smuzhiyun * @window_len: Number of registers in data window.
424*4882a593Smuzhiyun *
425*4882a593Smuzhiyun * Registers, mapped to this virtual range, are accessed in two steps:
426*4882a593Smuzhiyun * 1. page selector register update;
427*4882a593Smuzhiyun * 2. access through data window registers.
428*4882a593Smuzhiyun */
429*4882a593Smuzhiyun struct regmap_range_cfg {
430*4882a593Smuzhiyun const char *name;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /* Registers of virtual address range */
433*4882a593Smuzhiyun unsigned int range_min;
434*4882a593Smuzhiyun unsigned int range_max;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun /* Page selector for indirect addressing */
437*4882a593Smuzhiyun unsigned int selector_reg;
438*4882a593Smuzhiyun unsigned int selector_mask;
439*4882a593Smuzhiyun int selector_shift;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun /* Data window (per each page) */
442*4882a593Smuzhiyun unsigned int window_start;
443*4882a593Smuzhiyun unsigned int window_len;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun ANDROID_KABI_RESERVE(1);
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun struct regmap_async;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun typedef int (*regmap_hw_write)(void *context, const void *data,
451*4882a593Smuzhiyun size_t count);
452*4882a593Smuzhiyun typedef int (*regmap_hw_gather_write)(void *context,
453*4882a593Smuzhiyun const void *reg, size_t reg_len,
454*4882a593Smuzhiyun const void *val, size_t val_len);
455*4882a593Smuzhiyun typedef int (*regmap_hw_async_write)(void *context,
456*4882a593Smuzhiyun const void *reg, size_t reg_len,
457*4882a593Smuzhiyun const void *val, size_t val_len,
458*4882a593Smuzhiyun struct regmap_async *async);
459*4882a593Smuzhiyun typedef int (*regmap_hw_read)(void *context,
460*4882a593Smuzhiyun const void *reg_buf, size_t reg_size,
461*4882a593Smuzhiyun void *val_buf, size_t val_size);
462*4882a593Smuzhiyun typedef int (*regmap_hw_reg_read)(void *context, unsigned int reg,
463*4882a593Smuzhiyun unsigned int *val);
464*4882a593Smuzhiyun typedef int (*regmap_hw_reg_write)(void *context, unsigned int reg,
465*4882a593Smuzhiyun unsigned int val);
466*4882a593Smuzhiyun typedef int (*regmap_hw_reg_update_bits)(void *context, unsigned int reg,
467*4882a593Smuzhiyun unsigned int mask, unsigned int val);
468*4882a593Smuzhiyun typedef struct regmap_async *(*regmap_hw_async_alloc)(void);
469*4882a593Smuzhiyun typedef void (*regmap_hw_free_context)(void *context);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /**
472*4882a593Smuzhiyun * struct regmap_bus - Description of a hardware bus for the register map
473*4882a593Smuzhiyun * infrastructure.
474*4882a593Smuzhiyun *
475*4882a593Smuzhiyun * @fast_io: Register IO is fast. Use a spinlock instead of a mutex
476*4882a593Smuzhiyun * to perform locking. This field is ignored if custom lock/unlock
477*4882a593Smuzhiyun * functions are used (see fields lock/unlock of
478*4882a593Smuzhiyun * struct regmap_config).
479*4882a593Smuzhiyun * @write: Write operation.
480*4882a593Smuzhiyun * @gather_write: Write operation with split register/value, return -ENOTSUPP
481*4882a593Smuzhiyun * if not implemented on a given device.
482*4882a593Smuzhiyun * @async_write: Write operation which completes asynchronously, optional and
483*4882a593Smuzhiyun * must serialise with respect to non-async I/O.
484*4882a593Smuzhiyun * @reg_write: Write a single register value to the given register address. This
485*4882a593Smuzhiyun * write operation has to complete when returning from the function.
486*4882a593Smuzhiyun * @reg_update_bits: Update bits operation to be used against volatile
487*4882a593Smuzhiyun * registers, intended for devices supporting some mechanism
488*4882a593Smuzhiyun * for setting clearing bits without having to
489*4882a593Smuzhiyun * read/modify/write.
490*4882a593Smuzhiyun * @read: Read operation. Data is returned in the buffer used to transmit
491*4882a593Smuzhiyun * data.
492*4882a593Smuzhiyun * @reg_read: Read a single register value from a given register address.
493*4882a593Smuzhiyun * @free_context: Free context.
494*4882a593Smuzhiyun * @async_alloc: Allocate a regmap_async() structure.
495*4882a593Smuzhiyun * @read_flag_mask: Mask to be set in the top byte of the register when doing
496*4882a593Smuzhiyun * a read.
497*4882a593Smuzhiyun * @reg_format_endian_default: Default endianness for formatted register
498*4882a593Smuzhiyun * addresses. Used when the regmap_config specifies DEFAULT. If this is
499*4882a593Smuzhiyun * DEFAULT, BIG is assumed.
500*4882a593Smuzhiyun * @val_format_endian_default: Default endianness for formatted register
501*4882a593Smuzhiyun * values. Used when the regmap_config specifies DEFAULT. If this is
502*4882a593Smuzhiyun * DEFAULT, BIG is assumed.
503*4882a593Smuzhiyun * @max_raw_read: Max raw read size that can be used on the bus.
504*4882a593Smuzhiyun * @max_raw_write: Max raw write size that can be used on the bus.
505*4882a593Smuzhiyun */
506*4882a593Smuzhiyun struct regmap_bus {
507*4882a593Smuzhiyun bool fast_io;
508*4882a593Smuzhiyun regmap_hw_write write;
509*4882a593Smuzhiyun regmap_hw_gather_write gather_write;
510*4882a593Smuzhiyun regmap_hw_async_write async_write;
511*4882a593Smuzhiyun regmap_hw_reg_write reg_write;
512*4882a593Smuzhiyun regmap_hw_reg_update_bits reg_update_bits;
513*4882a593Smuzhiyun regmap_hw_read read;
514*4882a593Smuzhiyun regmap_hw_reg_read reg_read;
515*4882a593Smuzhiyun regmap_hw_free_context free_context;
516*4882a593Smuzhiyun regmap_hw_async_alloc async_alloc;
517*4882a593Smuzhiyun u8 read_flag_mask;
518*4882a593Smuzhiyun enum regmap_endian reg_format_endian_default;
519*4882a593Smuzhiyun enum regmap_endian val_format_endian_default;
520*4882a593Smuzhiyun size_t max_raw_read;
521*4882a593Smuzhiyun size_t max_raw_write;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun ANDROID_KABI_RESERVE(1);
524*4882a593Smuzhiyun };
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun /*
527*4882a593Smuzhiyun * __regmap_init functions.
528*4882a593Smuzhiyun *
529*4882a593Smuzhiyun * These functions take a lock key and name parameter, and should not be called
530*4882a593Smuzhiyun * directly. Instead, use the regmap_init macros that generate a key and name
531*4882a593Smuzhiyun * for each call.
532*4882a593Smuzhiyun */
533*4882a593Smuzhiyun struct regmap *__regmap_init(struct device *dev,
534*4882a593Smuzhiyun const struct regmap_bus *bus,
535*4882a593Smuzhiyun void *bus_context,
536*4882a593Smuzhiyun const struct regmap_config *config,
537*4882a593Smuzhiyun struct lock_class_key *lock_key,
538*4882a593Smuzhiyun const char *lock_name);
539*4882a593Smuzhiyun struct regmap *__regmap_init_i2c(struct i2c_client *i2c,
540*4882a593Smuzhiyun const struct regmap_config *config,
541*4882a593Smuzhiyun struct lock_class_key *lock_key,
542*4882a593Smuzhiyun const char *lock_name);
543*4882a593Smuzhiyun struct regmap *__regmap_init_sccb(struct i2c_client *i2c,
544*4882a593Smuzhiyun const struct regmap_config *config,
545*4882a593Smuzhiyun struct lock_class_key *lock_key,
546*4882a593Smuzhiyun const char *lock_name);
547*4882a593Smuzhiyun struct regmap *__regmap_init_slimbus(struct slim_device *slimbus,
548*4882a593Smuzhiyun const struct regmap_config *config,
549*4882a593Smuzhiyun struct lock_class_key *lock_key,
550*4882a593Smuzhiyun const char *lock_name);
551*4882a593Smuzhiyun struct regmap *__regmap_init_spi(struct spi_device *dev,
552*4882a593Smuzhiyun const struct regmap_config *config,
553*4882a593Smuzhiyun struct lock_class_key *lock_key,
554*4882a593Smuzhiyun const char *lock_name);
555*4882a593Smuzhiyun struct regmap *__regmap_init_spmi_base(struct spmi_device *dev,
556*4882a593Smuzhiyun const struct regmap_config *config,
557*4882a593Smuzhiyun struct lock_class_key *lock_key,
558*4882a593Smuzhiyun const char *lock_name);
559*4882a593Smuzhiyun struct regmap *__regmap_init_spmi_ext(struct spmi_device *dev,
560*4882a593Smuzhiyun const struct regmap_config *config,
561*4882a593Smuzhiyun struct lock_class_key *lock_key,
562*4882a593Smuzhiyun const char *lock_name);
563*4882a593Smuzhiyun struct regmap *__regmap_init_w1(struct device *w1_dev,
564*4882a593Smuzhiyun const struct regmap_config *config,
565*4882a593Smuzhiyun struct lock_class_key *lock_key,
566*4882a593Smuzhiyun const char *lock_name);
567*4882a593Smuzhiyun struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
568*4882a593Smuzhiyun void __iomem *regs,
569*4882a593Smuzhiyun const struct regmap_config *config,
570*4882a593Smuzhiyun struct lock_class_key *lock_key,
571*4882a593Smuzhiyun const char *lock_name);
572*4882a593Smuzhiyun struct regmap *__regmap_init_ac97(struct snd_ac97 *ac97,
573*4882a593Smuzhiyun const struct regmap_config *config,
574*4882a593Smuzhiyun struct lock_class_key *lock_key,
575*4882a593Smuzhiyun const char *lock_name);
576*4882a593Smuzhiyun struct regmap *__regmap_init_sdw(struct sdw_slave *sdw,
577*4882a593Smuzhiyun const struct regmap_config *config,
578*4882a593Smuzhiyun struct lock_class_key *lock_key,
579*4882a593Smuzhiyun const char *lock_name);
580*4882a593Smuzhiyun struct regmap *__regmap_init_spi_avmm(struct spi_device *spi,
581*4882a593Smuzhiyun const struct regmap_config *config,
582*4882a593Smuzhiyun struct lock_class_key *lock_key,
583*4882a593Smuzhiyun const char *lock_name);
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun struct regmap *__devm_regmap_init(struct device *dev,
586*4882a593Smuzhiyun const struct regmap_bus *bus,
587*4882a593Smuzhiyun void *bus_context,
588*4882a593Smuzhiyun const struct regmap_config *config,
589*4882a593Smuzhiyun struct lock_class_key *lock_key,
590*4882a593Smuzhiyun const char *lock_name);
591*4882a593Smuzhiyun struct regmap *__devm_regmap_init_i2c(struct i2c_client *i2c,
592*4882a593Smuzhiyun const struct regmap_config *config,
593*4882a593Smuzhiyun struct lock_class_key *lock_key,
594*4882a593Smuzhiyun const char *lock_name);
595*4882a593Smuzhiyun struct regmap *__devm_regmap_init_sccb(struct i2c_client *i2c,
596*4882a593Smuzhiyun const struct regmap_config *config,
597*4882a593Smuzhiyun struct lock_class_key *lock_key,
598*4882a593Smuzhiyun const char *lock_name);
599*4882a593Smuzhiyun struct regmap *__devm_regmap_init_spi(struct spi_device *dev,
600*4882a593Smuzhiyun const struct regmap_config *config,
601*4882a593Smuzhiyun struct lock_class_key *lock_key,
602*4882a593Smuzhiyun const char *lock_name);
603*4882a593Smuzhiyun struct regmap *__devm_regmap_init_spmi_base(struct spmi_device *dev,
604*4882a593Smuzhiyun const struct regmap_config *config,
605*4882a593Smuzhiyun struct lock_class_key *lock_key,
606*4882a593Smuzhiyun const char *lock_name);
607*4882a593Smuzhiyun struct regmap *__devm_regmap_init_spmi_ext(struct spmi_device *dev,
608*4882a593Smuzhiyun const struct regmap_config *config,
609*4882a593Smuzhiyun struct lock_class_key *lock_key,
610*4882a593Smuzhiyun const char *lock_name);
611*4882a593Smuzhiyun struct regmap *__devm_regmap_init_w1(struct device *w1_dev,
612*4882a593Smuzhiyun const struct regmap_config *config,
613*4882a593Smuzhiyun struct lock_class_key *lock_key,
614*4882a593Smuzhiyun const char *lock_name);
615*4882a593Smuzhiyun struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
616*4882a593Smuzhiyun const char *clk_id,
617*4882a593Smuzhiyun void __iomem *regs,
618*4882a593Smuzhiyun const struct regmap_config *config,
619*4882a593Smuzhiyun struct lock_class_key *lock_key,
620*4882a593Smuzhiyun const char *lock_name);
621*4882a593Smuzhiyun struct regmap *__devm_regmap_init_ac97(struct snd_ac97 *ac97,
622*4882a593Smuzhiyun const struct regmap_config *config,
623*4882a593Smuzhiyun struct lock_class_key *lock_key,
624*4882a593Smuzhiyun const char *lock_name);
625*4882a593Smuzhiyun struct regmap *__devm_regmap_init_sdw(struct sdw_slave *sdw,
626*4882a593Smuzhiyun const struct regmap_config *config,
627*4882a593Smuzhiyun struct lock_class_key *lock_key,
628*4882a593Smuzhiyun const char *lock_name);
629*4882a593Smuzhiyun struct regmap *__devm_regmap_init_slimbus(struct slim_device *slimbus,
630*4882a593Smuzhiyun const struct regmap_config *config,
631*4882a593Smuzhiyun struct lock_class_key *lock_key,
632*4882a593Smuzhiyun const char *lock_name);
633*4882a593Smuzhiyun struct regmap *__devm_regmap_init_i3c(struct i3c_device *i3c,
634*4882a593Smuzhiyun const struct regmap_config *config,
635*4882a593Smuzhiyun struct lock_class_key *lock_key,
636*4882a593Smuzhiyun const char *lock_name);
637*4882a593Smuzhiyun struct regmap *__devm_regmap_init_spi_avmm(struct spi_device *spi,
638*4882a593Smuzhiyun const struct regmap_config *config,
639*4882a593Smuzhiyun struct lock_class_key *lock_key,
640*4882a593Smuzhiyun const char *lock_name);
641*4882a593Smuzhiyun /*
642*4882a593Smuzhiyun * Wrapper for regmap_init macros to include a unique lockdep key and name
643*4882a593Smuzhiyun * for each call. No-op if CONFIG_LOCKDEP is not set.
644*4882a593Smuzhiyun *
645*4882a593Smuzhiyun * @fn: Real function to call (in the form __[*_]regmap_init[_*])
646*4882a593Smuzhiyun * @name: Config variable name (#config in the calling macro)
647*4882a593Smuzhiyun **/
648*4882a593Smuzhiyun #ifdef CONFIG_LOCKDEP
649*4882a593Smuzhiyun #define __regmap_lockdep_wrapper(fn, name, ...) \
650*4882a593Smuzhiyun ( \
651*4882a593Smuzhiyun ({ \
652*4882a593Smuzhiyun static struct lock_class_key _key; \
653*4882a593Smuzhiyun fn(__VA_ARGS__, &_key, \
654*4882a593Smuzhiyun KBUILD_BASENAME ":" \
655*4882a593Smuzhiyun __stringify(__LINE__) ":" \
656*4882a593Smuzhiyun "(" name ")->lock"); \
657*4882a593Smuzhiyun }) \
658*4882a593Smuzhiyun )
659*4882a593Smuzhiyun #else
660*4882a593Smuzhiyun #define __regmap_lockdep_wrapper(fn, name, ...) fn(__VA_ARGS__, NULL, NULL)
661*4882a593Smuzhiyun #endif
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun /**
664*4882a593Smuzhiyun * regmap_init() - Initialise register map
665*4882a593Smuzhiyun *
666*4882a593Smuzhiyun * @dev: Device that will be interacted with
667*4882a593Smuzhiyun * @bus: Bus-specific callbacks to use with device
668*4882a593Smuzhiyun * @bus_context: Data passed to bus-specific callbacks
669*4882a593Smuzhiyun * @config: Configuration for register map
670*4882a593Smuzhiyun *
671*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
672*4882a593Smuzhiyun * a struct regmap. This function should generally not be called
673*4882a593Smuzhiyun * directly, it should be called by bus-specific init functions.
674*4882a593Smuzhiyun */
675*4882a593Smuzhiyun #define regmap_init(dev, bus, bus_context, config) \
676*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init, #config, \
677*4882a593Smuzhiyun dev, bus, bus_context, config)
678*4882a593Smuzhiyun int regmap_attach_dev(struct device *dev, struct regmap *map,
679*4882a593Smuzhiyun const struct regmap_config *config);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun /**
682*4882a593Smuzhiyun * regmap_init_i2c() - Initialise register map
683*4882a593Smuzhiyun *
684*4882a593Smuzhiyun * @i2c: Device that will be interacted with
685*4882a593Smuzhiyun * @config: Configuration for register map
686*4882a593Smuzhiyun *
687*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
688*4882a593Smuzhiyun * a struct regmap.
689*4882a593Smuzhiyun */
690*4882a593Smuzhiyun #define regmap_init_i2c(i2c, config) \
691*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_i2c, #config, \
692*4882a593Smuzhiyun i2c, config)
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun /**
695*4882a593Smuzhiyun * regmap_init_sccb() - Initialise register map
696*4882a593Smuzhiyun *
697*4882a593Smuzhiyun * @i2c: Device that will be interacted with
698*4882a593Smuzhiyun * @config: Configuration for register map
699*4882a593Smuzhiyun *
700*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
701*4882a593Smuzhiyun * a struct regmap.
702*4882a593Smuzhiyun */
703*4882a593Smuzhiyun #define regmap_init_sccb(i2c, config) \
704*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_sccb, #config, \
705*4882a593Smuzhiyun i2c, config)
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun /**
708*4882a593Smuzhiyun * regmap_init_slimbus() - Initialise register map
709*4882a593Smuzhiyun *
710*4882a593Smuzhiyun * @slimbus: Device that will be interacted with
711*4882a593Smuzhiyun * @config: Configuration for register map
712*4882a593Smuzhiyun *
713*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
714*4882a593Smuzhiyun * a struct regmap.
715*4882a593Smuzhiyun */
716*4882a593Smuzhiyun #define regmap_init_slimbus(slimbus, config) \
717*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_slimbus, #config, \
718*4882a593Smuzhiyun slimbus, config)
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun /**
721*4882a593Smuzhiyun * regmap_init_spi() - Initialise register map
722*4882a593Smuzhiyun *
723*4882a593Smuzhiyun * @dev: Device that will be interacted with
724*4882a593Smuzhiyun * @config: Configuration for register map
725*4882a593Smuzhiyun *
726*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
727*4882a593Smuzhiyun * a struct regmap.
728*4882a593Smuzhiyun */
729*4882a593Smuzhiyun #define regmap_init_spi(dev, config) \
730*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_spi, #config, \
731*4882a593Smuzhiyun dev, config)
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun /**
734*4882a593Smuzhiyun * regmap_init_spmi_base() - Create regmap for the Base register space
735*4882a593Smuzhiyun *
736*4882a593Smuzhiyun * @dev: SPMI device that will be interacted with
737*4882a593Smuzhiyun * @config: Configuration for register map
738*4882a593Smuzhiyun *
739*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
740*4882a593Smuzhiyun * a struct regmap.
741*4882a593Smuzhiyun */
742*4882a593Smuzhiyun #define regmap_init_spmi_base(dev, config) \
743*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_spmi_base, #config, \
744*4882a593Smuzhiyun dev, config)
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun /**
747*4882a593Smuzhiyun * regmap_init_spmi_ext() - Create regmap for Ext register space
748*4882a593Smuzhiyun *
749*4882a593Smuzhiyun * @dev: Device that will be interacted with
750*4882a593Smuzhiyun * @config: Configuration for register map
751*4882a593Smuzhiyun *
752*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
753*4882a593Smuzhiyun * a struct regmap.
754*4882a593Smuzhiyun */
755*4882a593Smuzhiyun #define regmap_init_spmi_ext(dev, config) \
756*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_spmi_ext, #config, \
757*4882a593Smuzhiyun dev, config)
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun /**
760*4882a593Smuzhiyun * regmap_init_w1() - Initialise register map
761*4882a593Smuzhiyun *
762*4882a593Smuzhiyun * @w1_dev: Device that will be interacted with
763*4882a593Smuzhiyun * @config: Configuration for register map
764*4882a593Smuzhiyun *
765*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
766*4882a593Smuzhiyun * a struct regmap.
767*4882a593Smuzhiyun */
768*4882a593Smuzhiyun #define regmap_init_w1(w1_dev, config) \
769*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_w1, #config, \
770*4882a593Smuzhiyun w1_dev, config)
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun /**
773*4882a593Smuzhiyun * regmap_init_mmio_clk() - Initialise register map with register clock
774*4882a593Smuzhiyun *
775*4882a593Smuzhiyun * @dev: Device that will be interacted with
776*4882a593Smuzhiyun * @clk_id: register clock consumer ID
777*4882a593Smuzhiyun * @regs: Pointer to memory-mapped IO region
778*4882a593Smuzhiyun * @config: Configuration for register map
779*4882a593Smuzhiyun *
780*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
781*4882a593Smuzhiyun * a struct regmap.
782*4882a593Smuzhiyun */
783*4882a593Smuzhiyun #define regmap_init_mmio_clk(dev, clk_id, regs, config) \
784*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_mmio_clk, #config, \
785*4882a593Smuzhiyun dev, clk_id, regs, config)
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun /**
788*4882a593Smuzhiyun * regmap_init_mmio() - Initialise register map
789*4882a593Smuzhiyun *
790*4882a593Smuzhiyun * @dev: Device that will be interacted with
791*4882a593Smuzhiyun * @regs: Pointer to memory-mapped IO region
792*4882a593Smuzhiyun * @config: Configuration for register map
793*4882a593Smuzhiyun *
794*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
795*4882a593Smuzhiyun * a struct regmap.
796*4882a593Smuzhiyun */
797*4882a593Smuzhiyun #define regmap_init_mmio(dev, regs, config) \
798*4882a593Smuzhiyun regmap_init_mmio_clk(dev, NULL, regs, config)
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun /**
801*4882a593Smuzhiyun * regmap_init_ac97() - Initialise AC'97 register map
802*4882a593Smuzhiyun *
803*4882a593Smuzhiyun * @ac97: Device that will be interacted with
804*4882a593Smuzhiyun * @config: Configuration for register map
805*4882a593Smuzhiyun *
806*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
807*4882a593Smuzhiyun * a struct regmap.
808*4882a593Smuzhiyun */
809*4882a593Smuzhiyun #define regmap_init_ac97(ac97, config) \
810*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_ac97, #config, \
811*4882a593Smuzhiyun ac97, config)
812*4882a593Smuzhiyun bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg);
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun /**
815*4882a593Smuzhiyun * regmap_init_sdw() - Initialise register map
816*4882a593Smuzhiyun *
817*4882a593Smuzhiyun * @sdw: Device that will be interacted with
818*4882a593Smuzhiyun * @config: Configuration for register map
819*4882a593Smuzhiyun *
820*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer to
821*4882a593Smuzhiyun * a struct regmap.
822*4882a593Smuzhiyun */
823*4882a593Smuzhiyun #define regmap_init_sdw(sdw, config) \
824*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_sdw, #config, \
825*4882a593Smuzhiyun sdw, config)
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun /**
828*4882a593Smuzhiyun * regmap_init_spi_avmm() - Initialize register map for Intel SPI Slave
829*4882a593Smuzhiyun * to AVMM Bus Bridge
830*4882a593Smuzhiyun *
831*4882a593Smuzhiyun * @spi: Device that will be interacted with
832*4882a593Smuzhiyun * @config: Configuration for register map
833*4882a593Smuzhiyun *
834*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
835*4882a593Smuzhiyun * to a struct regmap.
836*4882a593Smuzhiyun */
837*4882a593Smuzhiyun #define regmap_init_spi_avmm(spi, config) \
838*4882a593Smuzhiyun __regmap_lockdep_wrapper(__regmap_init_spi_avmm, #config, \
839*4882a593Smuzhiyun spi, config)
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun /**
842*4882a593Smuzhiyun * devm_regmap_init() - Initialise managed register map
843*4882a593Smuzhiyun *
844*4882a593Smuzhiyun * @dev: Device that will be interacted with
845*4882a593Smuzhiyun * @bus: Bus-specific callbacks to use with device
846*4882a593Smuzhiyun * @bus_context: Data passed to bus-specific callbacks
847*4882a593Smuzhiyun * @config: Configuration for register map
848*4882a593Smuzhiyun *
849*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
850*4882a593Smuzhiyun * to a struct regmap. This function should generally not be called
851*4882a593Smuzhiyun * directly, it should be called by bus-specific init functions. The
852*4882a593Smuzhiyun * map will be automatically freed by the device management code.
853*4882a593Smuzhiyun */
854*4882a593Smuzhiyun #define devm_regmap_init(dev, bus, bus_context, config) \
855*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init, #config, \
856*4882a593Smuzhiyun dev, bus, bus_context, config)
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun /**
859*4882a593Smuzhiyun * devm_regmap_init_i2c() - Initialise managed register map
860*4882a593Smuzhiyun *
861*4882a593Smuzhiyun * @i2c: Device that will be interacted with
862*4882a593Smuzhiyun * @config: Configuration for register map
863*4882a593Smuzhiyun *
864*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
865*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
866*4882a593Smuzhiyun * device management code.
867*4882a593Smuzhiyun */
868*4882a593Smuzhiyun #define devm_regmap_init_i2c(i2c, config) \
869*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_i2c, #config, \
870*4882a593Smuzhiyun i2c, config)
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun /**
873*4882a593Smuzhiyun * devm_regmap_init_sccb() - Initialise managed register map
874*4882a593Smuzhiyun *
875*4882a593Smuzhiyun * @i2c: Device that will be interacted with
876*4882a593Smuzhiyun * @config: Configuration for register map
877*4882a593Smuzhiyun *
878*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
879*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
880*4882a593Smuzhiyun * device management code.
881*4882a593Smuzhiyun */
882*4882a593Smuzhiyun #define devm_regmap_init_sccb(i2c, config) \
883*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_sccb, #config, \
884*4882a593Smuzhiyun i2c, config)
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun /**
887*4882a593Smuzhiyun * devm_regmap_init_spi() - Initialise register map
888*4882a593Smuzhiyun *
889*4882a593Smuzhiyun * @dev: Device that will be interacted with
890*4882a593Smuzhiyun * @config: Configuration for register map
891*4882a593Smuzhiyun *
892*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
893*4882a593Smuzhiyun * to a struct regmap. The map will be automatically freed by the
894*4882a593Smuzhiyun * device management code.
895*4882a593Smuzhiyun */
896*4882a593Smuzhiyun #define devm_regmap_init_spi(dev, config) \
897*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_spi, #config, \
898*4882a593Smuzhiyun dev, config)
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun /**
901*4882a593Smuzhiyun * devm_regmap_init_spmi_base() - Create managed regmap for Base register space
902*4882a593Smuzhiyun *
903*4882a593Smuzhiyun * @dev: SPMI device that will be interacted with
904*4882a593Smuzhiyun * @config: Configuration for register map
905*4882a593Smuzhiyun *
906*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
907*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
908*4882a593Smuzhiyun * device management code.
909*4882a593Smuzhiyun */
910*4882a593Smuzhiyun #define devm_regmap_init_spmi_base(dev, config) \
911*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_spmi_base, #config, \
912*4882a593Smuzhiyun dev, config)
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun /**
915*4882a593Smuzhiyun * devm_regmap_init_spmi_ext() - Create managed regmap for Ext register space
916*4882a593Smuzhiyun *
917*4882a593Smuzhiyun * @dev: SPMI device that will be interacted with
918*4882a593Smuzhiyun * @config: Configuration for register map
919*4882a593Smuzhiyun *
920*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
921*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
922*4882a593Smuzhiyun * device management code.
923*4882a593Smuzhiyun */
924*4882a593Smuzhiyun #define devm_regmap_init_spmi_ext(dev, config) \
925*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_spmi_ext, #config, \
926*4882a593Smuzhiyun dev, config)
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun /**
929*4882a593Smuzhiyun * devm_regmap_init_w1() - Initialise managed register map
930*4882a593Smuzhiyun *
931*4882a593Smuzhiyun * @w1_dev: Device that will be interacted with
932*4882a593Smuzhiyun * @config: Configuration for register map
933*4882a593Smuzhiyun *
934*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
935*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
936*4882a593Smuzhiyun * device management code.
937*4882a593Smuzhiyun */
938*4882a593Smuzhiyun #define devm_regmap_init_w1(w1_dev, config) \
939*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_w1, #config, \
940*4882a593Smuzhiyun w1_dev, config)
941*4882a593Smuzhiyun /**
942*4882a593Smuzhiyun * devm_regmap_init_mmio_clk() - Initialise managed register map with clock
943*4882a593Smuzhiyun *
944*4882a593Smuzhiyun * @dev: Device that will be interacted with
945*4882a593Smuzhiyun * @clk_id: register clock consumer ID
946*4882a593Smuzhiyun * @regs: Pointer to memory-mapped IO region
947*4882a593Smuzhiyun * @config: Configuration for register map
948*4882a593Smuzhiyun *
949*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
950*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
951*4882a593Smuzhiyun * device management code.
952*4882a593Smuzhiyun */
953*4882a593Smuzhiyun #define devm_regmap_init_mmio_clk(dev, clk_id, regs, config) \
954*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_mmio_clk, #config, \
955*4882a593Smuzhiyun dev, clk_id, regs, config)
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun /**
958*4882a593Smuzhiyun * devm_regmap_init_mmio() - Initialise managed register map
959*4882a593Smuzhiyun *
960*4882a593Smuzhiyun * @dev: Device that will be interacted with
961*4882a593Smuzhiyun * @regs: Pointer to memory-mapped IO region
962*4882a593Smuzhiyun * @config: Configuration for register map
963*4882a593Smuzhiyun *
964*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
965*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
966*4882a593Smuzhiyun * device management code.
967*4882a593Smuzhiyun */
968*4882a593Smuzhiyun #define devm_regmap_init_mmio(dev, regs, config) \
969*4882a593Smuzhiyun devm_regmap_init_mmio_clk(dev, NULL, regs, config)
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun /**
972*4882a593Smuzhiyun * devm_regmap_init_ac97() - Initialise AC'97 register map
973*4882a593Smuzhiyun *
974*4882a593Smuzhiyun * @ac97: Device that will be interacted with
975*4882a593Smuzhiyun * @config: Configuration for register map
976*4882a593Smuzhiyun *
977*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
978*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
979*4882a593Smuzhiyun * device management code.
980*4882a593Smuzhiyun */
981*4882a593Smuzhiyun #define devm_regmap_init_ac97(ac97, config) \
982*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_ac97, #config, \
983*4882a593Smuzhiyun ac97, config)
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun /**
986*4882a593Smuzhiyun * devm_regmap_init_sdw() - Initialise managed register map
987*4882a593Smuzhiyun *
988*4882a593Smuzhiyun * @sdw: Device that will be interacted with
989*4882a593Smuzhiyun * @config: Configuration for register map
990*4882a593Smuzhiyun *
991*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
992*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
993*4882a593Smuzhiyun * device management code.
994*4882a593Smuzhiyun */
995*4882a593Smuzhiyun #define devm_regmap_init_sdw(sdw, config) \
996*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_sdw, #config, \
997*4882a593Smuzhiyun sdw, config)
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun /**
1000*4882a593Smuzhiyun * devm_regmap_init_slimbus() - Initialise managed register map
1001*4882a593Smuzhiyun *
1002*4882a593Smuzhiyun * @slimbus: Device that will be interacted with
1003*4882a593Smuzhiyun * @config: Configuration for register map
1004*4882a593Smuzhiyun *
1005*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
1006*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
1007*4882a593Smuzhiyun * device management code.
1008*4882a593Smuzhiyun */
1009*4882a593Smuzhiyun #define devm_regmap_init_slimbus(slimbus, config) \
1010*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_slimbus, #config, \
1011*4882a593Smuzhiyun slimbus, config)
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun /**
1014*4882a593Smuzhiyun * devm_regmap_init_i3c() - Initialise managed register map
1015*4882a593Smuzhiyun *
1016*4882a593Smuzhiyun * @i3c: Device that will be interacted with
1017*4882a593Smuzhiyun * @config: Configuration for register map
1018*4882a593Smuzhiyun *
1019*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
1020*4882a593Smuzhiyun * to a struct regmap. The regmap will be automatically freed by the
1021*4882a593Smuzhiyun * device management code.
1022*4882a593Smuzhiyun */
1023*4882a593Smuzhiyun #define devm_regmap_init_i3c(i3c, config) \
1024*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_i3c, #config, \
1025*4882a593Smuzhiyun i3c, config)
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun /**
1028*4882a593Smuzhiyun * devm_regmap_init_spi_avmm() - Initialize register map for Intel SPI Slave
1029*4882a593Smuzhiyun * to AVMM Bus Bridge
1030*4882a593Smuzhiyun *
1031*4882a593Smuzhiyun * @spi: Device that will be interacted with
1032*4882a593Smuzhiyun * @config: Configuration for register map
1033*4882a593Smuzhiyun *
1034*4882a593Smuzhiyun * The return value will be an ERR_PTR() on error or a valid pointer
1035*4882a593Smuzhiyun * to a struct regmap. The map will be automatically freed by the
1036*4882a593Smuzhiyun * device management code.
1037*4882a593Smuzhiyun */
1038*4882a593Smuzhiyun #define devm_regmap_init_spi_avmm(spi, config) \
1039*4882a593Smuzhiyun __regmap_lockdep_wrapper(__devm_regmap_init_spi_avmm, #config, \
1040*4882a593Smuzhiyun spi, config)
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk);
1043*4882a593Smuzhiyun void regmap_mmio_detach_clk(struct regmap *map);
1044*4882a593Smuzhiyun void regmap_exit(struct regmap *map);
1045*4882a593Smuzhiyun int regmap_reinit_cache(struct regmap *map,
1046*4882a593Smuzhiyun const struct regmap_config *config);
1047*4882a593Smuzhiyun struct regmap *dev_get_regmap(struct device *dev, const char *name);
1048*4882a593Smuzhiyun struct device *regmap_get_device(struct regmap *map);
1049*4882a593Smuzhiyun int regmap_write(struct regmap *map, unsigned int reg, unsigned int val);
1050*4882a593Smuzhiyun int regmap_write_async(struct regmap *map, unsigned int reg, unsigned int val);
1051*4882a593Smuzhiyun int regmap_raw_write(struct regmap *map, unsigned int reg,
1052*4882a593Smuzhiyun const void *val, size_t val_len);
1053*4882a593Smuzhiyun int regmap_noinc_write(struct regmap *map, unsigned int reg,
1054*4882a593Smuzhiyun const void *val, size_t val_len);
1055*4882a593Smuzhiyun int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val,
1056*4882a593Smuzhiyun size_t val_count);
1057*4882a593Smuzhiyun int regmap_multi_reg_write(struct regmap *map, const struct reg_sequence *regs,
1058*4882a593Smuzhiyun int num_regs);
1059*4882a593Smuzhiyun int regmap_multi_reg_write_bypassed(struct regmap *map,
1060*4882a593Smuzhiyun const struct reg_sequence *regs,
1061*4882a593Smuzhiyun int num_regs);
1062*4882a593Smuzhiyun int regmap_raw_write_async(struct regmap *map, unsigned int reg,
1063*4882a593Smuzhiyun const void *val, size_t val_len);
1064*4882a593Smuzhiyun int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val);
1065*4882a593Smuzhiyun int regmap_raw_read(struct regmap *map, unsigned int reg,
1066*4882a593Smuzhiyun void *val, size_t val_len);
1067*4882a593Smuzhiyun int regmap_noinc_read(struct regmap *map, unsigned int reg,
1068*4882a593Smuzhiyun void *val, size_t val_len);
1069*4882a593Smuzhiyun int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
1070*4882a593Smuzhiyun size_t val_count);
1071*4882a593Smuzhiyun int regmap_update_bits_base(struct regmap *map, unsigned int reg,
1072*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1073*4882a593Smuzhiyun bool *change, bool async, bool force);
1074*4882a593Smuzhiyun
regmap_update_bits(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val)1075*4882a593Smuzhiyun static inline int regmap_update_bits(struct regmap *map, unsigned int reg,
1076*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1077*4882a593Smuzhiyun {
1078*4882a593Smuzhiyun return regmap_update_bits_base(map, reg, mask, val, NULL, false, false);
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun
regmap_update_bits_async(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val)1081*4882a593Smuzhiyun static inline int regmap_update_bits_async(struct regmap *map, unsigned int reg,
1082*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1083*4882a593Smuzhiyun {
1084*4882a593Smuzhiyun return regmap_update_bits_base(map, reg, mask, val, NULL, true, false);
1085*4882a593Smuzhiyun }
1086*4882a593Smuzhiyun
regmap_update_bits_check(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change)1087*4882a593Smuzhiyun static inline int regmap_update_bits_check(struct regmap *map, unsigned int reg,
1088*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1089*4882a593Smuzhiyun bool *change)
1090*4882a593Smuzhiyun {
1091*4882a593Smuzhiyun return regmap_update_bits_base(map, reg, mask, val,
1092*4882a593Smuzhiyun change, false, false);
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun static inline int
regmap_update_bits_check_async(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change)1096*4882a593Smuzhiyun regmap_update_bits_check_async(struct regmap *map, unsigned int reg,
1097*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1098*4882a593Smuzhiyun bool *change)
1099*4882a593Smuzhiyun {
1100*4882a593Smuzhiyun return regmap_update_bits_base(map, reg, mask, val,
1101*4882a593Smuzhiyun change, true, false);
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun
regmap_write_bits(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val)1104*4882a593Smuzhiyun static inline int regmap_write_bits(struct regmap *map, unsigned int reg,
1105*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1106*4882a593Smuzhiyun {
1107*4882a593Smuzhiyun return regmap_update_bits_base(map, reg, mask, val, NULL, false, true);
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun int regmap_get_val_bytes(struct regmap *map);
1111*4882a593Smuzhiyun int regmap_get_max_register(struct regmap *map);
1112*4882a593Smuzhiyun int regmap_get_reg_stride(struct regmap *map);
1113*4882a593Smuzhiyun int regmap_async_complete(struct regmap *map);
1114*4882a593Smuzhiyun bool regmap_can_raw_write(struct regmap *map);
1115*4882a593Smuzhiyun size_t regmap_get_raw_read_max(struct regmap *map);
1116*4882a593Smuzhiyun size_t regmap_get_raw_write_max(struct regmap *map);
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun int regcache_sync(struct regmap *map);
1119*4882a593Smuzhiyun int regcache_sync_region(struct regmap *map, unsigned int min,
1120*4882a593Smuzhiyun unsigned int max);
1121*4882a593Smuzhiyun int regcache_drop_region(struct regmap *map, unsigned int min,
1122*4882a593Smuzhiyun unsigned int max);
1123*4882a593Smuzhiyun void regcache_cache_only(struct regmap *map, bool enable);
1124*4882a593Smuzhiyun void regcache_cache_bypass(struct regmap *map, bool enable);
1125*4882a593Smuzhiyun void regcache_mark_dirty(struct regmap *map);
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun bool regmap_check_range_table(struct regmap *map, unsigned int reg,
1128*4882a593Smuzhiyun const struct regmap_access_table *table);
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun int regmap_register_patch(struct regmap *map, const struct reg_sequence *regs,
1131*4882a593Smuzhiyun int num_regs);
1132*4882a593Smuzhiyun int regmap_parse_val(struct regmap *map, const void *buf,
1133*4882a593Smuzhiyun unsigned int *val);
1134*4882a593Smuzhiyun
regmap_reg_in_range(unsigned int reg,const struct regmap_range * range)1135*4882a593Smuzhiyun static inline bool regmap_reg_in_range(unsigned int reg,
1136*4882a593Smuzhiyun const struct regmap_range *range)
1137*4882a593Smuzhiyun {
1138*4882a593Smuzhiyun return reg >= range->range_min && reg <= range->range_max;
1139*4882a593Smuzhiyun }
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun bool regmap_reg_in_ranges(unsigned int reg,
1142*4882a593Smuzhiyun const struct regmap_range *ranges,
1143*4882a593Smuzhiyun unsigned int nranges);
1144*4882a593Smuzhiyun
regmap_set_bits(struct regmap * map,unsigned int reg,unsigned int bits)1145*4882a593Smuzhiyun static inline int regmap_set_bits(struct regmap *map,
1146*4882a593Smuzhiyun unsigned int reg, unsigned int bits)
1147*4882a593Smuzhiyun {
1148*4882a593Smuzhiyun return regmap_update_bits_base(map, reg, bits, bits,
1149*4882a593Smuzhiyun NULL, false, false);
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun
regmap_clear_bits(struct regmap * map,unsigned int reg,unsigned int bits)1152*4882a593Smuzhiyun static inline int regmap_clear_bits(struct regmap *map,
1153*4882a593Smuzhiyun unsigned int reg, unsigned int bits)
1154*4882a593Smuzhiyun {
1155*4882a593Smuzhiyun return regmap_update_bits_base(map, reg, bits, 0, NULL, false, false);
1156*4882a593Smuzhiyun }
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun int regmap_test_bits(struct regmap *map, unsigned int reg, unsigned int bits);
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun /**
1161*4882a593Smuzhiyun * struct reg_field - Description of an register field
1162*4882a593Smuzhiyun *
1163*4882a593Smuzhiyun * @reg: Offset of the register within the regmap bank
1164*4882a593Smuzhiyun * @lsb: lsb of the register field.
1165*4882a593Smuzhiyun * @msb: msb of the register field.
1166*4882a593Smuzhiyun * @id_size: port size if it has some ports
1167*4882a593Smuzhiyun * @id_offset: address offset for each ports
1168*4882a593Smuzhiyun */
1169*4882a593Smuzhiyun struct reg_field {
1170*4882a593Smuzhiyun unsigned int reg;
1171*4882a593Smuzhiyun unsigned int lsb;
1172*4882a593Smuzhiyun unsigned int msb;
1173*4882a593Smuzhiyun unsigned int id_size;
1174*4882a593Smuzhiyun unsigned int id_offset;
1175*4882a593Smuzhiyun };
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun #define REG_FIELD(_reg, _lsb, _msb) { \
1178*4882a593Smuzhiyun .reg = _reg, \
1179*4882a593Smuzhiyun .lsb = _lsb, \
1180*4882a593Smuzhiyun .msb = _msb, \
1181*4882a593Smuzhiyun }
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun #define REG_FIELD_ID(_reg, _lsb, _msb, _size, _offset) { \
1184*4882a593Smuzhiyun .reg = _reg, \
1185*4882a593Smuzhiyun .lsb = _lsb, \
1186*4882a593Smuzhiyun .msb = _msb, \
1187*4882a593Smuzhiyun .id_size = _size, \
1188*4882a593Smuzhiyun .id_offset = _offset, \
1189*4882a593Smuzhiyun }
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun struct regmap_field *regmap_field_alloc(struct regmap *regmap,
1192*4882a593Smuzhiyun struct reg_field reg_field);
1193*4882a593Smuzhiyun void regmap_field_free(struct regmap_field *field);
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun struct regmap_field *devm_regmap_field_alloc(struct device *dev,
1196*4882a593Smuzhiyun struct regmap *regmap, struct reg_field reg_field);
1197*4882a593Smuzhiyun void devm_regmap_field_free(struct device *dev, struct regmap_field *field);
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun int regmap_field_bulk_alloc(struct regmap *regmap,
1200*4882a593Smuzhiyun struct regmap_field **rm_field,
1201*4882a593Smuzhiyun struct reg_field *reg_field,
1202*4882a593Smuzhiyun int num_fields);
1203*4882a593Smuzhiyun void regmap_field_bulk_free(struct regmap_field *field);
1204*4882a593Smuzhiyun int devm_regmap_field_bulk_alloc(struct device *dev, struct regmap *regmap,
1205*4882a593Smuzhiyun struct regmap_field **field,
1206*4882a593Smuzhiyun struct reg_field *reg_field, int num_fields);
1207*4882a593Smuzhiyun void devm_regmap_field_bulk_free(struct device *dev,
1208*4882a593Smuzhiyun struct regmap_field *field);
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun int regmap_field_read(struct regmap_field *field, unsigned int *val);
1211*4882a593Smuzhiyun int regmap_field_update_bits_base(struct regmap_field *field,
1212*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1213*4882a593Smuzhiyun bool *change, bool async, bool force);
1214*4882a593Smuzhiyun int regmap_fields_read(struct regmap_field *field, unsigned int id,
1215*4882a593Smuzhiyun unsigned int *val);
1216*4882a593Smuzhiyun int regmap_fields_update_bits_base(struct regmap_field *field, unsigned int id,
1217*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1218*4882a593Smuzhiyun bool *change, bool async, bool force);
1219*4882a593Smuzhiyun
regmap_field_write(struct regmap_field * field,unsigned int val)1220*4882a593Smuzhiyun static inline int regmap_field_write(struct regmap_field *field,
1221*4882a593Smuzhiyun unsigned int val)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun return regmap_field_update_bits_base(field, ~0, val,
1224*4882a593Smuzhiyun NULL, false, false);
1225*4882a593Smuzhiyun }
1226*4882a593Smuzhiyun
regmap_field_force_write(struct regmap_field * field,unsigned int val)1227*4882a593Smuzhiyun static inline int regmap_field_force_write(struct regmap_field *field,
1228*4882a593Smuzhiyun unsigned int val)
1229*4882a593Smuzhiyun {
1230*4882a593Smuzhiyun return regmap_field_update_bits_base(field, ~0, val, NULL, false, true);
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun
regmap_field_update_bits(struct regmap_field * field,unsigned int mask,unsigned int val)1233*4882a593Smuzhiyun static inline int regmap_field_update_bits(struct regmap_field *field,
1234*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1235*4882a593Smuzhiyun {
1236*4882a593Smuzhiyun return regmap_field_update_bits_base(field, mask, val,
1237*4882a593Smuzhiyun NULL, false, false);
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun static inline int
regmap_field_force_update_bits(struct regmap_field * field,unsigned int mask,unsigned int val)1241*4882a593Smuzhiyun regmap_field_force_update_bits(struct regmap_field *field,
1242*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1243*4882a593Smuzhiyun {
1244*4882a593Smuzhiyun return regmap_field_update_bits_base(field, mask, val,
1245*4882a593Smuzhiyun NULL, false, true);
1246*4882a593Smuzhiyun }
1247*4882a593Smuzhiyun
regmap_fields_write(struct regmap_field * field,unsigned int id,unsigned int val)1248*4882a593Smuzhiyun static inline int regmap_fields_write(struct regmap_field *field,
1249*4882a593Smuzhiyun unsigned int id, unsigned int val)
1250*4882a593Smuzhiyun {
1251*4882a593Smuzhiyun return regmap_fields_update_bits_base(field, id, ~0, val,
1252*4882a593Smuzhiyun NULL, false, false);
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun
regmap_fields_force_write(struct regmap_field * field,unsigned int id,unsigned int val)1255*4882a593Smuzhiyun static inline int regmap_fields_force_write(struct regmap_field *field,
1256*4882a593Smuzhiyun unsigned int id, unsigned int val)
1257*4882a593Smuzhiyun {
1258*4882a593Smuzhiyun return regmap_fields_update_bits_base(field, id, ~0, val,
1259*4882a593Smuzhiyun NULL, false, true);
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun static inline int
regmap_fields_update_bits(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val)1263*4882a593Smuzhiyun regmap_fields_update_bits(struct regmap_field *field, unsigned int id,
1264*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1265*4882a593Smuzhiyun {
1266*4882a593Smuzhiyun return regmap_fields_update_bits_base(field, id, mask, val,
1267*4882a593Smuzhiyun NULL, false, false);
1268*4882a593Smuzhiyun }
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun static inline int
regmap_fields_force_update_bits(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val)1271*4882a593Smuzhiyun regmap_fields_force_update_bits(struct regmap_field *field, unsigned int id,
1272*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1273*4882a593Smuzhiyun {
1274*4882a593Smuzhiyun return regmap_fields_update_bits_base(field, id, mask, val,
1275*4882a593Smuzhiyun NULL, false, true);
1276*4882a593Smuzhiyun }
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun /**
1279*4882a593Smuzhiyun * struct regmap_irq_type - IRQ type definitions.
1280*4882a593Smuzhiyun *
1281*4882a593Smuzhiyun * @type_reg_offset: Offset register for the irq type setting.
1282*4882a593Smuzhiyun * @type_rising_val: Register value to configure RISING type irq.
1283*4882a593Smuzhiyun * @type_falling_val: Register value to configure FALLING type irq.
1284*4882a593Smuzhiyun * @type_level_low_val: Register value to configure LEVEL_LOW type irq.
1285*4882a593Smuzhiyun * @type_level_high_val: Register value to configure LEVEL_HIGH type irq.
1286*4882a593Smuzhiyun * @types_supported: logical OR of IRQ_TYPE_* flags indicating supported types.
1287*4882a593Smuzhiyun */
1288*4882a593Smuzhiyun struct regmap_irq_type {
1289*4882a593Smuzhiyun unsigned int type_reg_offset;
1290*4882a593Smuzhiyun unsigned int type_reg_mask;
1291*4882a593Smuzhiyun unsigned int type_rising_val;
1292*4882a593Smuzhiyun unsigned int type_falling_val;
1293*4882a593Smuzhiyun unsigned int type_level_low_val;
1294*4882a593Smuzhiyun unsigned int type_level_high_val;
1295*4882a593Smuzhiyun unsigned int types_supported;
1296*4882a593Smuzhiyun };
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun /**
1299*4882a593Smuzhiyun * struct regmap_irq - Description of an IRQ for the generic regmap irq_chip.
1300*4882a593Smuzhiyun *
1301*4882a593Smuzhiyun * @reg_offset: Offset of the status/mask register within the bank
1302*4882a593Smuzhiyun * @mask: Mask used to flag/control the register.
1303*4882a593Smuzhiyun * @type: IRQ trigger type setting details if supported.
1304*4882a593Smuzhiyun */
1305*4882a593Smuzhiyun struct regmap_irq {
1306*4882a593Smuzhiyun unsigned int reg_offset;
1307*4882a593Smuzhiyun unsigned int mask;
1308*4882a593Smuzhiyun struct regmap_irq_type type;
1309*4882a593Smuzhiyun };
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun #define REGMAP_IRQ_REG(_irq, _off, _mask) \
1312*4882a593Smuzhiyun [_irq] = { .reg_offset = (_off), .mask = (_mask) }
1313*4882a593Smuzhiyun
1314*4882a593Smuzhiyun #define REGMAP_IRQ_REG_LINE(_id, _reg_bits) \
1315*4882a593Smuzhiyun [_id] = { \
1316*4882a593Smuzhiyun .mask = BIT((_id) % (_reg_bits)), \
1317*4882a593Smuzhiyun .reg_offset = (_id) / (_reg_bits), \
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun #define REGMAP_IRQ_MAIN_REG_OFFSET(arr) \
1321*4882a593Smuzhiyun { .num_regs = ARRAY_SIZE((arr)), .offset = &(arr)[0] }
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun struct regmap_irq_sub_irq_map {
1324*4882a593Smuzhiyun unsigned int num_regs;
1325*4882a593Smuzhiyun unsigned int *offset;
1326*4882a593Smuzhiyun };
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun /**
1329*4882a593Smuzhiyun * struct regmap_irq_chip - Description of a generic regmap irq_chip.
1330*4882a593Smuzhiyun *
1331*4882a593Smuzhiyun * @name: Descriptive name for IRQ controller.
1332*4882a593Smuzhiyun *
1333*4882a593Smuzhiyun * @main_status: Base main status register address. For chips which have
1334*4882a593Smuzhiyun * interrupts arranged in separate sub-irq blocks with own IRQ
1335*4882a593Smuzhiyun * registers and which have a main IRQ registers indicating
1336*4882a593Smuzhiyun * sub-irq blocks with unhandled interrupts. For such chips fill
1337*4882a593Smuzhiyun * sub-irq register information in status_base, mask_base and
1338*4882a593Smuzhiyun * ack_base.
1339*4882a593Smuzhiyun * @num_main_status_bits: Should be given to chips where number of meaningfull
1340*4882a593Smuzhiyun * main status bits differs from num_regs.
1341*4882a593Smuzhiyun * @sub_reg_offsets: arrays of mappings from main register bits to sub irq
1342*4882a593Smuzhiyun * registers. First item in array describes the registers
1343*4882a593Smuzhiyun * for first main status bit. Second array for second bit etc.
1344*4882a593Smuzhiyun * Offset is given as sub register status offset to
1345*4882a593Smuzhiyun * status_base. Should contain num_regs arrays.
1346*4882a593Smuzhiyun * Can be provided for chips with more complex mapping than
1347*4882a593Smuzhiyun * 1.st bit to 1.st sub-reg, 2.nd bit to 2.nd sub-reg, ...
1348*4882a593Smuzhiyun * @num_main_regs: Number of 'main status' irq registers for chips which have
1349*4882a593Smuzhiyun * main_status set.
1350*4882a593Smuzhiyun *
1351*4882a593Smuzhiyun * @status_base: Base status register address.
1352*4882a593Smuzhiyun * @mask_base: Base mask register address.
1353*4882a593Smuzhiyun * @mask_writeonly: Base mask register is write only.
1354*4882a593Smuzhiyun * @unmask_base: Base unmask register address. for chips who have
1355*4882a593Smuzhiyun * separate mask and unmask registers
1356*4882a593Smuzhiyun * @ack_base: Base ack address. If zero then the chip is clear on read.
1357*4882a593Smuzhiyun * Using zero value is possible with @use_ack bit.
1358*4882a593Smuzhiyun * @wake_base: Base address for wake enables. If zero unsupported.
1359*4882a593Smuzhiyun * @type_base: Base address for irq type. If zero unsupported.
1360*4882a593Smuzhiyun * @irq_reg_stride: Stride to use for chips where registers are not contiguous.
1361*4882a593Smuzhiyun * @init_ack_masked: Ack all masked interrupts once during initalization.
1362*4882a593Smuzhiyun * @mask_invert: Inverted mask register: cleared bits are masked out.
1363*4882a593Smuzhiyun * @use_ack: Use @ack register even if it is zero.
1364*4882a593Smuzhiyun * @ack_invert: Inverted ack register: cleared bits for ack.
1365*4882a593Smuzhiyun * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts.
1366*4882a593Smuzhiyun * @wake_invert: Inverted wake register: cleared bits are wake enabled.
1367*4882a593Smuzhiyun * @type_invert: Invert the type flags.
1368*4882a593Smuzhiyun * @type_in_mask: Use the mask registers for controlling irq type. For
1369*4882a593Smuzhiyun * interrupts defining type_rising/falling_mask use mask_base
1370*4882a593Smuzhiyun * for edge configuration and never update bits in type_base.
1371*4882a593Smuzhiyun * @clear_on_unmask: For chips with interrupts cleared on read: read the status
1372*4882a593Smuzhiyun * registers before unmasking interrupts to clear any bits
1373*4882a593Smuzhiyun * set when they were masked.
1374*4882a593Smuzhiyun * @runtime_pm: Hold a runtime PM lock on the device when accessing it.
1375*4882a593Smuzhiyun *
1376*4882a593Smuzhiyun * @num_regs: Number of registers in each control bank.
1377*4882a593Smuzhiyun * @irqs: Descriptors for individual IRQs. Interrupt numbers are
1378*4882a593Smuzhiyun * assigned based on the index in the array of the interrupt.
1379*4882a593Smuzhiyun * @num_irqs: Number of descriptors.
1380*4882a593Smuzhiyun * @num_type_reg: Number of type registers.
1381*4882a593Smuzhiyun * @type_reg_stride: Stride to use for chips where type registers are not
1382*4882a593Smuzhiyun * contiguous.
1383*4882a593Smuzhiyun * @handle_pre_irq: Driver specific callback to handle interrupt from device
1384*4882a593Smuzhiyun * before regmap_irq_handler process the interrupts.
1385*4882a593Smuzhiyun * @handle_post_irq: Driver specific callback to handle interrupt from device
1386*4882a593Smuzhiyun * after handling the interrupts in regmap_irq_handler().
1387*4882a593Smuzhiyun * @irq_drv_data: Driver specific IRQ data which is passed as parameter when
1388*4882a593Smuzhiyun * driver specific pre/post interrupt handler is called.
1389*4882a593Smuzhiyun *
1390*4882a593Smuzhiyun * This is not intended to handle every possible interrupt controller, but
1391*4882a593Smuzhiyun * it should handle a substantial proportion of those that are found in the
1392*4882a593Smuzhiyun * wild.
1393*4882a593Smuzhiyun */
1394*4882a593Smuzhiyun struct regmap_irq_chip {
1395*4882a593Smuzhiyun const char *name;
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun unsigned int main_status;
1398*4882a593Smuzhiyun unsigned int num_main_status_bits;
1399*4882a593Smuzhiyun struct regmap_irq_sub_irq_map *sub_reg_offsets;
1400*4882a593Smuzhiyun int num_main_regs;
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun unsigned int status_base;
1403*4882a593Smuzhiyun unsigned int mask_base;
1404*4882a593Smuzhiyun unsigned int unmask_base;
1405*4882a593Smuzhiyun unsigned int ack_base;
1406*4882a593Smuzhiyun unsigned int wake_base;
1407*4882a593Smuzhiyun unsigned int type_base;
1408*4882a593Smuzhiyun unsigned int irq_reg_stride;
1409*4882a593Smuzhiyun bool mask_writeonly:1;
1410*4882a593Smuzhiyun bool init_ack_masked:1;
1411*4882a593Smuzhiyun bool mask_invert:1;
1412*4882a593Smuzhiyun bool use_ack:1;
1413*4882a593Smuzhiyun bool ack_invert:1;
1414*4882a593Smuzhiyun bool clear_ack:1;
1415*4882a593Smuzhiyun bool wake_invert:1;
1416*4882a593Smuzhiyun bool runtime_pm:1;
1417*4882a593Smuzhiyun bool type_invert:1;
1418*4882a593Smuzhiyun bool type_in_mask:1;
1419*4882a593Smuzhiyun bool clear_on_unmask:1;
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun int num_regs;
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun const struct regmap_irq *irqs;
1424*4882a593Smuzhiyun int num_irqs;
1425*4882a593Smuzhiyun
1426*4882a593Smuzhiyun int num_type_reg;
1427*4882a593Smuzhiyun unsigned int type_reg_stride;
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun int (*handle_pre_irq)(void *irq_drv_data);
1430*4882a593Smuzhiyun int (*handle_post_irq)(void *irq_drv_data);
1431*4882a593Smuzhiyun void *irq_drv_data;
1432*4882a593Smuzhiyun };
1433*4882a593Smuzhiyun
1434*4882a593Smuzhiyun struct regmap_irq_chip_data;
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
1437*4882a593Smuzhiyun int irq_base, const struct regmap_irq_chip *chip,
1438*4882a593Smuzhiyun struct regmap_irq_chip_data **data);
1439*4882a593Smuzhiyun int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode,
1440*4882a593Smuzhiyun struct regmap *map, int irq,
1441*4882a593Smuzhiyun int irq_flags, int irq_base,
1442*4882a593Smuzhiyun const struct regmap_irq_chip *chip,
1443*4882a593Smuzhiyun struct regmap_irq_chip_data **data);
1444*4882a593Smuzhiyun void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data);
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
1447*4882a593Smuzhiyun int irq_flags, int irq_base,
1448*4882a593Smuzhiyun const struct regmap_irq_chip *chip,
1449*4882a593Smuzhiyun struct regmap_irq_chip_data **data);
1450*4882a593Smuzhiyun int devm_regmap_add_irq_chip_fwnode(struct device *dev,
1451*4882a593Smuzhiyun struct fwnode_handle *fwnode,
1452*4882a593Smuzhiyun struct regmap *map, int irq,
1453*4882a593Smuzhiyun int irq_flags, int irq_base,
1454*4882a593Smuzhiyun const struct regmap_irq_chip *chip,
1455*4882a593Smuzhiyun struct regmap_irq_chip_data **data);
1456*4882a593Smuzhiyun void devm_regmap_del_irq_chip(struct device *dev, int irq,
1457*4882a593Smuzhiyun struct regmap_irq_chip_data *data);
1458*4882a593Smuzhiyun
1459*4882a593Smuzhiyun int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data);
1460*4882a593Smuzhiyun int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq);
1461*4882a593Smuzhiyun struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data);
1462*4882a593Smuzhiyun
1463*4882a593Smuzhiyun #else
1464*4882a593Smuzhiyun
1465*4882a593Smuzhiyun /*
1466*4882a593Smuzhiyun * These stubs should only ever be called by generic code which has
1467*4882a593Smuzhiyun * regmap based facilities, if they ever get called at runtime
1468*4882a593Smuzhiyun * something is going wrong and something probably needs to select
1469*4882a593Smuzhiyun * REGMAP.
1470*4882a593Smuzhiyun */
1471*4882a593Smuzhiyun
regmap_write(struct regmap * map,unsigned int reg,unsigned int val)1472*4882a593Smuzhiyun static inline int regmap_write(struct regmap *map, unsigned int reg,
1473*4882a593Smuzhiyun unsigned int val)
1474*4882a593Smuzhiyun {
1475*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1476*4882a593Smuzhiyun return -EINVAL;
1477*4882a593Smuzhiyun }
1478*4882a593Smuzhiyun
regmap_write_async(struct regmap * map,unsigned int reg,unsigned int val)1479*4882a593Smuzhiyun static inline int regmap_write_async(struct regmap *map, unsigned int reg,
1480*4882a593Smuzhiyun unsigned int val)
1481*4882a593Smuzhiyun {
1482*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1483*4882a593Smuzhiyun return -EINVAL;
1484*4882a593Smuzhiyun }
1485*4882a593Smuzhiyun
regmap_raw_write(struct regmap * map,unsigned int reg,const void * val,size_t val_len)1486*4882a593Smuzhiyun static inline int regmap_raw_write(struct regmap *map, unsigned int reg,
1487*4882a593Smuzhiyun const void *val, size_t val_len)
1488*4882a593Smuzhiyun {
1489*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1490*4882a593Smuzhiyun return -EINVAL;
1491*4882a593Smuzhiyun }
1492*4882a593Smuzhiyun
regmap_raw_write_async(struct regmap * map,unsigned int reg,const void * val,size_t val_len)1493*4882a593Smuzhiyun static inline int regmap_raw_write_async(struct regmap *map, unsigned int reg,
1494*4882a593Smuzhiyun const void *val, size_t val_len)
1495*4882a593Smuzhiyun {
1496*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1497*4882a593Smuzhiyun return -EINVAL;
1498*4882a593Smuzhiyun }
1499*4882a593Smuzhiyun
regmap_noinc_write(struct regmap * map,unsigned int reg,const void * val,size_t val_len)1500*4882a593Smuzhiyun static inline int regmap_noinc_write(struct regmap *map, unsigned int reg,
1501*4882a593Smuzhiyun const void *val, size_t val_len)
1502*4882a593Smuzhiyun {
1503*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1504*4882a593Smuzhiyun return -EINVAL;
1505*4882a593Smuzhiyun }
1506*4882a593Smuzhiyun
regmap_bulk_write(struct regmap * map,unsigned int reg,const void * val,size_t val_count)1507*4882a593Smuzhiyun static inline int regmap_bulk_write(struct regmap *map, unsigned int reg,
1508*4882a593Smuzhiyun const void *val, size_t val_count)
1509*4882a593Smuzhiyun {
1510*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1511*4882a593Smuzhiyun return -EINVAL;
1512*4882a593Smuzhiyun }
1513*4882a593Smuzhiyun
regmap_read(struct regmap * map,unsigned int reg,unsigned int * val)1514*4882a593Smuzhiyun static inline int regmap_read(struct regmap *map, unsigned int reg,
1515*4882a593Smuzhiyun unsigned int *val)
1516*4882a593Smuzhiyun {
1517*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1518*4882a593Smuzhiyun return -EINVAL;
1519*4882a593Smuzhiyun }
1520*4882a593Smuzhiyun
regmap_raw_read(struct regmap * map,unsigned int reg,void * val,size_t val_len)1521*4882a593Smuzhiyun static inline int regmap_raw_read(struct regmap *map, unsigned int reg,
1522*4882a593Smuzhiyun void *val, size_t val_len)
1523*4882a593Smuzhiyun {
1524*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1525*4882a593Smuzhiyun return -EINVAL;
1526*4882a593Smuzhiyun }
1527*4882a593Smuzhiyun
regmap_noinc_read(struct regmap * map,unsigned int reg,void * val,size_t val_len)1528*4882a593Smuzhiyun static inline int regmap_noinc_read(struct regmap *map, unsigned int reg,
1529*4882a593Smuzhiyun void *val, size_t val_len)
1530*4882a593Smuzhiyun {
1531*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1532*4882a593Smuzhiyun return -EINVAL;
1533*4882a593Smuzhiyun }
1534*4882a593Smuzhiyun
regmap_bulk_read(struct regmap * map,unsigned int reg,void * val,size_t val_count)1535*4882a593Smuzhiyun static inline int regmap_bulk_read(struct regmap *map, unsigned int reg,
1536*4882a593Smuzhiyun void *val, size_t val_count)
1537*4882a593Smuzhiyun {
1538*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1539*4882a593Smuzhiyun return -EINVAL;
1540*4882a593Smuzhiyun }
1541*4882a593Smuzhiyun
regmap_update_bits_base(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change,bool async,bool force)1542*4882a593Smuzhiyun static inline int regmap_update_bits_base(struct regmap *map, unsigned int reg,
1543*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1544*4882a593Smuzhiyun bool *change, bool async, bool force)
1545*4882a593Smuzhiyun {
1546*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1547*4882a593Smuzhiyun return -EINVAL;
1548*4882a593Smuzhiyun }
1549*4882a593Smuzhiyun
regmap_set_bits(struct regmap * map,unsigned int reg,unsigned int bits)1550*4882a593Smuzhiyun static inline int regmap_set_bits(struct regmap *map,
1551*4882a593Smuzhiyun unsigned int reg, unsigned int bits)
1552*4882a593Smuzhiyun {
1553*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1554*4882a593Smuzhiyun return -EINVAL;
1555*4882a593Smuzhiyun }
1556*4882a593Smuzhiyun
regmap_clear_bits(struct regmap * map,unsigned int reg,unsigned int bits)1557*4882a593Smuzhiyun static inline int regmap_clear_bits(struct regmap *map,
1558*4882a593Smuzhiyun unsigned int reg, unsigned int bits)
1559*4882a593Smuzhiyun {
1560*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1561*4882a593Smuzhiyun return -EINVAL;
1562*4882a593Smuzhiyun }
1563*4882a593Smuzhiyun
regmap_test_bits(struct regmap * map,unsigned int reg,unsigned int bits)1564*4882a593Smuzhiyun static inline int regmap_test_bits(struct regmap *map,
1565*4882a593Smuzhiyun unsigned int reg, unsigned int bits)
1566*4882a593Smuzhiyun {
1567*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1568*4882a593Smuzhiyun return -EINVAL;
1569*4882a593Smuzhiyun }
1570*4882a593Smuzhiyun
regmap_field_update_bits_base(struct regmap_field * field,unsigned int mask,unsigned int val,bool * change,bool async,bool force)1571*4882a593Smuzhiyun static inline int regmap_field_update_bits_base(struct regmap_field *field,
1572*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1573*4882a593Smuzhiyun bool *change, bool async, bool force)
1574*4882a593Smuzhiyun {
1575*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1576*4882a593Smuzhiyun return -EINVAL;
1577*4882a593Smuzhiyun }
1578*4882a593Smuzhiyun
regmap_fields_update_bits_base(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val,bool * change,bool async,bool force)1579*4882a593Smuzhiyun static inline int regmap_fields_update_bits_base(struct regmap_field *field,
1580*4882a593Smuzhiyun unsigned int id,
1581*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1582*4882a593Smuzhiyun bool *change, bool async, bool force)
1583*4882a593Smuzhiyun {
1584*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1585*4882a593Smuzhiyun return -EINVAL;
1586*4882a593Smuzhiyun }
1587*4882a593Smuzhiyun
regmap_update_bits(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val)1588*4882a593Smuzhiyun static inline int regmap_update_bits(struct regmap *map, unsigned int reg,
1589*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1590*4882a593Smuzhiyun {
1591*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1592*4882a593Smuzhiyun return -EINVAL;
1593*4882a593Smuzhiyun }
1594*4882a593Smuzhiyun
regmap_update_bits_async(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val)1595*4882a593Smuzhiyun static inline int regmap_update_bits_async(struct regmap *map, unsigned int reg,
1596*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1597*4882a593Smuzhiyun {
1598*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1599*4882a593Smuzhiyun return -EINVAL;
1600*4882a593Smuzhiyun }
1601*4882a593Smuzhiyun
regmap_update_bits_check(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change)1602*4882a593Smuzhiyun static inline int regmap_update_bits_check(struct regmap *map, unsigned int reg,
1603*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1604*4882a593Smuzhiyun bool *change)
1605*4882a593Smuzhiyun {
1606*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1607*4882a593Smuzhiyun return -EINVAL;
1608*4882a593Smuzhiyun }
1609*4882a593Smuzhiyun
1610*4882a593Smuzhiyun static inline int
regmap_update_bits_check_async(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change)1611*4882a593Smuzhiyun regmap_update_bits_check_async(struct regmap *map, unsigned int reg,
1612*4882a593Smuzhiyun unsigned int mask, unsigned int val,
1613*4882a593Smuzhiyun bool *change)
1614*4882a593Smuzhiyun {
1615*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1616*4882a593Smuzhiyun return -EINVAL;
1617*4882a593Smuzhiyun }
1618*4882a593Smuzhiyun
regmap_write_bits(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val)1619*4882a593Smuzhiyun static inline int regmap_write_bits(struct regmap *map, unsigned int reg,
1620*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1621*4882a593Smuzhiyun {
1622*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1623*4882a593Smuzhiyun return -EINVAL;
1624*4882a593Smuzhiyun }
1625*4882a593Smuzhiyun
regmap_field_write(struct regmap_field * field,unsigned int val)1626*4882a593Smuzhiyun static inline int regmap_field_write(struct regmap_field *field,
1627*4882a593Smuzhiyun unsigned int val)
1628*4882a593Smuzhiyun {
1629*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1630*4882a593Smuzhiyun return -EINVAL;
1631*4882a593Smuzhiyun }
1632*4882a593Smuzhiyun
regmap_field_force_write(struct regmap_field * field,unsigned int val)1633*4882a593Smuzhiyun static inline int regmap_field_force_write(struct regmap_field *field,
1634*4882a593Smuzhiyun unsigned int val)
1635*4882a593Smuzhiyun {
1636*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1637*4882a593Smuzhiyun return -EINVAL;
1638*4882a593Smuzhiyun }
1639*4882a593Smuzhiyun
regmap_field_update_bits(struct regmap_field * field,unsigned int mask,unsigned int val)1640*4882a593Smuzhiyun static inline int regmap_field_update_bits(struct regmap_field *field,
1641*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1642*4882a593Smuzhiyun {
1643*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1644*4882a593Smuzhiyun return -EINVAL;
1645*4882a593Smuzhiyun }
1646*4882a593Smuzhiyun
1647*4882a593Smuzhiyun static inline int
regmap_field_force_update_bits(struct regmap_field * field,unsigned int mask,unsigned int val)1648*4882a593Smuzhiyun regmap_field_force_update_bits(struct regmap_field *field,
1649*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1650*4882a593Smuzhiyun {
1651*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1652*4882a593Smuzhiyun return -EINVAL;
1653*4882a593Smuzhiyun }
1654*4882a593Smuzhiyun
regmap_fields_write(struct regmap_field * field,unsigned int id,unsigned int val)1655*4882a593Smuzhiyun static inline int regmap_fields_write(struct regmap_field *field,
1656*4882a593Smuzhiyun unsigned int id, unsigned int val)
1657*4882a593Smuzhiyun {
1658*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1659*4882a593Smuzhiyun return -EINVAL;
1660*4882a593Smuzhiyun }
1661*4882a593Smuzhiyun
regmap_fields_force_write(struct regmap_field * field,unsigned int id,unsigned int val)1662*4882a593Smuzhiyun static inline int regmap_fields_force_write(struct regmap_field *field,
1663*4882a593Smuzhiyun unsigned int id, unsigned int val)
1664*4882a593Smuzhiyun {
1665*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1666*4882a593Smuzhiyun return -EINVAL;
1667*4882a593Smuzhiyun }
1668*4882a593Smuzhiyun
1669*4882a593Smuzhiyun static inline int
regmap_fields_update_bits(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val)1670*4882a593Smuzhiyun regmap_fields_update_bits(struct regmap_field *field, unsigned int id,
1671*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1672*4882a593Smuzhiyun {
1673*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1674*4882a593Smuzhiyun return -EINVAL;
1675*4882a593Smuzhiyun }
1676*4882a593Smuzhiyun
1677*4882a593Smuzhiyun static inline int
regmap_fields_force_update_bits(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val)1678*4882a593Smuzhiyun regmap_fields_force_update_bits(struct regmap_field *field, unsigned int id,
1679*4882a593Smuzhiyun unsigned int mask, unsigned int val)
1680*4882a593Smuzhiyun {
1681*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1682*4882a593Smuzhiyun return -EINVAL;
1683*4882a593Smuzhiyun }
1684*4882a593Smuzhiyun
regmap_get_val_bytes(struct regmap * map)1685*4882a593Smuzhiyun static inline int regmap_get_val_bytes(struct regmap *map)
1686*4882a593Smuzhiyun {
1687*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1688*4882a593Smuzhiyun return -EINVAL;
1689*4882a593Smuzhiyun }
1690*4882a593Smuzhiyun
regmap_get_max_register(struct regmap * map)1691*4882a593Smuzhiyun static inline int regmap_get_max_register(struct regmap *map)
1692*4882a593Smuzhiyun {
1693*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1694*4882a593Smuzhiyun return -EINVAL;
1695*4882a593Smuzhiyun }
1696*4882a593Smuzhiyun
regmap_get_reg_stride(struct regmap * map)1697*4882a593Smuzhiyun static inline int regmap_get_reg_stride(struct regmap *map)
1698*4882a593Smuzhiyun {
1699*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1700*4882a593Smuzhiyun return -EINVAL;
1701*4882a593Smuzhiyun }
1702*4882a593Smuzhiyun
regcache_sync(struct regmap * map)1703*4882a593Smuzhiyun static inline int regcache_sync(struct regmap *map)
1704*4882a593Smuzhiyun {
1705*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1706*4882a593Smuzhiyun return -EINVAL;
1707*4882a593Smuzhiyun }
1708*4882a593Smuzhiyun
regcache_sync_region(struct regmap * map,unsigned int min,unsigned int max)1709*4882a593Smuzhiyun static inline int regcache_sync_region(struct regmap *map, unsigned int min,
1710*4882a593Smuzhiyun unsigned int max)
1711*4882a593Smuzhiyun {
1712*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1713*4882a593Smuzhiyun return -EINVAL;
1714*4882a593Smuzhiyun }
1715*4882a593Smuzhiyun
regcache_drop_region(struct regmap * map,unsigned int min,unsigned int max)1716*4882a593Smuzhiyun static inline int regcache_drop_region(struct regmap *map, unsigned int min,
1717*4882a593Smuzhiyun unsigned int max)
1718*4882a593Smuzhiyun {
1719*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1720*4882a593Smuzhiyun return -EINVAL;
1721*4882a593Smuzhiyun }
1722*4882a593Smuzhiyun
regcache_cache_only(struct regmap * map,bool enable)1723*4882a593Smuzhiyun static inline void regcache_cache_only(struct regmap *map, bool enable)
1724*4882a593Smuzhiyun {
1725*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1726*4882a593Smuzhiyun }
1727*4882a593Smuzhiyun
regcache_cache_bypass(struct regmap * map,bool enable)1728*4882a593Smuzhiyun static inline void regcache_cache_bypass(struct regmap *map, bool enable)
1729*4882a593Smuzhiyun {
1730*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1731*4882a593Smuzhiyun }
1732*4882a593Smuzhiyun
regcache_mark_dirty(struct regmap * map)1733*4882a593Smuzhiyun static inline void regcache_mark_dirty(struct regmap *map)
1734*4882a593Smuzhiyun {
1735*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1736*4882a593Smuzhiyun }
1737*4882a593Smuzhiyun
regmap_async_complete(struct regmap * map)1738*4882a593Smuzhiyun static inline void regmap_async_complete(struct regmap *map)
1739*4882a593Smuzhiyun {
1740*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1741*4882a593Smuzhiyun }
1742*4882a593Smuzhiyun
regmap_register_patch(struct regmap * map,const struct reg_sequence * regs,int num_regs)1743*4882a593Smuzhiyun static inline int regmap_register_patch(struct regmap *map,
1744*4882a593Smuzhiyun const struct reg_sequence *regs,
1745*4882a593Smuzhiyun int num_regs)
1746*4882a593Smuzhiyun {
1747*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1748*4882a593Smuzhiyun return -EINVAL;
1749*4882a593Smuzhiyun }
1750*4882a593Smuzhiyun
regmap_parse_val(struct regmap * map,const void * buf,unsigned int * val)1751*4882a593Smuzhiyun static inline int regmap_parse_val(struct regmap *map, const void *buf,
1752*4882a593Smuzhiyun unsigned int *val)
1753*4882a593Smuzhiyun {
1754*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1755*4882a593Smuzhiyun return -EINVAL;
1756*4882a593Smuzhiyun }
1757*4882a593Smuzhiyun
dev_get_regmap(struct device * dev,const char * name)1758*4882a593Smuzhiyun static inline struct regmap *dev_get_regmap(struct device *dev,
1759*4882a593Smuzhiyun const char *name)
1760*4882a593Smuzhiyun {
1761*4882a593Smuzhiyun return NULL;
1762*4882a593Smuzhiyun }
1763*4882a593Smuzhiyun
regmap_get_device(struct regmap * map)1764*4882a593Smuzhiyun static inline struct device *regmap_get_device(struct regmap *map)
1765*4882a593Smuzhiyun {
1766*4882a593Smuzhiyun WARN_ONCE(1, "regmap API is disabled");
1767*4882a593Smuzhiyun return NULL;
1768*4882a593Smuzhiyun }
1769*4882a593Smuzhiyun
1770*4882a593Smuzhiyun #endif
1771*4882a593Smuzhiyun
1772*4882a593Smuzhiyun #endif
1773