1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __LINUX_XILINX_LL_TEMAC_H 3*4882a593Smuzhiyun #define __LINUX_XILINX_LL_TEMAC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/if_ether.h> 6*4882a593Smuzhiyun #include <linux/phy.h> 7*4882a593Smuzhiyun #include <linux/spinlock.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct ll_temac_platform_data { 10*4882a593Smuzhiyun bool txcsum; /* Enable/disable TX checksum */ 11*4882a593Smuzhiyun bool rxcsum; /* Enable/disable RX checksum */ 12*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; /* MAC address (6 bytes) */ 13*4882a593Smuzhiyun /* Clock frequency for input to MDIO clock generator */ 14*4882a593Smuzhiyun u32 mdio_clk_freq; 15*4882a593Smuzhiyun unsigned long long mdio_bus_id; /* Unique id for MDIO bus */ 16*4882a593Smuzhiyun int phy_addr; /* Address of the PHY to connect to */ 17*4882a593Smuzhiyun phy_interface_t phy_interface; /* PHY interface mode */ 18*4882a593Smuzhiyun bool reg_little_endian; /* Little endian TEMAC register access */ 19*4882a593Smuzhiyun bool dma_little_endian; /* Little endian DMA register access */ 20*4882a593Smuzhiyun /* Pre-initialized mutex to use for synchronizing indirect 21*4882a593Smuzhiyun * register access. When using both interfaces of a single 22*4882a593Smuzhiyun * TEMAC IP block, the same mutex should be passed here, as 23*4882a593Smuzhiyun * they share the same DCR bus bridge. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun spinlock_t *indirect_lock; 26*4882a593Smuzhiyun /* DMA channel control setup */ 27*4882a593Smuzhiyun u8 tx_irq_timeout; /* TX Interrupt Delay Time-out */ 28*4882a593Smuzhiyun u8 tx_irq_count; /* TX Interrupt Coalescing Threshold Count */ 29*4882a593Smuzhiyun u8 rx_irq_timeout; /* RX Interrupt Delay Time-out */ 30*4882a593Smuzhiyun u8 rx_irq_count; /* RX Interrupt Coalescing Threshold Count */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __LINUX_XILINX_LL_TEMAC_H */ 34