1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Intel Atom platform clocks for BayTrail and CherryTrail SoC. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016, Intel Corporation 6*4882a593Smuzhiyun * Author: Irina Tirdea <irina.tirdea@intel.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H 10*4882a593Smuzhiyun #define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * struct pmc_clk - PMC platform clock configuration 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * @name: identified, typically pmc_plt_clk_<x>, x=[0..5] 16*4882a593Smuzhiyun * @freq: in Hz, 19.2MHz and 25MHz (Baytrail only) supported 17*4882a593Smuzhiyun * @parent_name: one of 'xtal' or 'osc' 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun struct pmc_clk { 20*4882a593Smuzhiyun const char *name; 21*4882a593Smuzhiyun unsigned long freq; 22*4882a593Smuzhiyun const char *parent_name; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /** 26*4882a593Smuzhiyun * struct pmc_clk_data - common PMC clock configuration 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * @base: PMC clock register base offset 29*4882a593Smuzhiyun * @clks: pointer to set of registered clocks, typically 0..5 30*4882a593Smuzhiyun * @critical: flag to indicate if firmware enabled pmc_plt_clks 31*4882a593Smuzhiyun * should be marked as critial or not 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun struct pmc_clk_data { 34*4882a593Smuzhiyun void __iomem *base; 35*4882a593Smuzhiyun const struct pmc_clk *clks; 36*4882a593Smuzhiyun bool critical; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */ 40