1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef ASMARM_ARCH_OHCI_H 3*4882a593Smuzhiyun #define ASMARM_ARCH_OHCI_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun struct device; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct pxaohci_platform_data { 8*4882a593Smuzhiyun int (*init)(struct device *); 9*4882a593Smuzhiyun void (*exit)(struct device *); 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun unsigned long flags; 12*4882a593Smuzhiyun #define ENABLE_PORT1 (1 << 0) 13*4882a593Smuzhiyun #define ENABLE_PORT2 (1 << 1) 14*4882a593Smuzhiyun #define ENABLE_PORT3 (1 << 2) 15*4882a593Smuzhiyun #define ENABLE_PORT_ALL (ENABLE_PORT1 | ENABLE_PORT2 | ENABLE_PORT3) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define POWER_SENSE_LOW (1 << 3) 18*4882a593Smuzhiyun #define POWER_CONTROL_LOW (1 << 4) 19*4882a593Smuzhiyun #define NO_OC_PROTECTION (1 << 5) 20*4882a593Smuzhiyun #define OC_MODE_GLOBAL (0 << 6) 21*4882a593Smuzhiyun #define OC_MODE_PERPORT (1 << 6) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun int power_on_delay; /* Power On to Power Good time - in ms 24*4882a593Smuzhiyun * HCD must wait for this duration before 25*4882a593Smuzhiyun * accessing a powered on port 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun int port_mode; 28*4882a593Smuzhiyun #define PMM_NPS_MODE 1 29*4882a593Smuzhiyun #define PMM_GLOBAL_MODE 2 30*4882a593Smuzhiyun #define PMM_PERPORT_MODE 3 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun int power_budget; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun extern void pxa_set_ohci_info(struct pxaohci_platform_data *info); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif 38