1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright TOSHIBA CORPORATION 2007 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __TXX9_NDFMC_H 7*4882a593Smuzhiyun #define __TXX9_NDFMC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define NDFMC_PLAT_FLAG_USE_BSPRT 0x01 10*4882a593Smuzhiyun #define NDFMC_PLAT_FLAG_NO_RSTR 0x02 11*4882a593Smuzhiyun #define NDFMC_PLAT_FLAG_HOLDADD 0x04 12*4882a593Smuzhiyun #define NDFMC_PLAT_FLAG_DUMMYWRITE 0x08 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct txx9ndfmc_platform_data { 15*4882a593Smuzhiyun unsigned int shift; 16*4882a593Smuzhiyun unsigned int gbus_clock; 17*4882a593Smuzhiyun unsigned int hold; /* hold time in nanosecond */ 18*4882a593Smuzhiyun unsigned int spw; /* strobe pulse width in nanosecond */ 19*4882a593Smuzhiyun unsigned int flags; 20*4882a593Smuzhiyun unsigned char ch_mask; /* available channel bitmask */ 21*4882a593Smuzhiyun unsigned char wp_mask; /* write-protect bitmask */ 22*4882a593Smuzhiyun unsigned char wide_mask; /* 16bit-nand bitmask */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun void txx9_ndfmc_init(unsigned long baseaddr, 26*4882a593Smuzhiyun const struct txx9ndfmc_platform_data *plat_data); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* __TXX9_NDFMC_H */ 29