1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _OMAP2_MCSPI_H 3*4882a593Smuzhiyun #define _OMAP2_MCSPI_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define OMAP4_MCSPI_REG_OFFSET 0x100 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define MCSPI_PINDIR_D0_IN_D1_OUT 0 8*4882a593Smuzhiyun #define MCSPI_PINDIR_D0_OUT_D1_IN 1 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct omap2_mcspi_platform_config { 11*4882a593Smuzhiyun unsigned short num_cs; 12*4882a593Smuzhiyun unsigned int regs_offset; 13*4882a593Smuzhiyun unsigned int pin_dir:1; 14*4882a593Smuzhiyun size_t max_xfer_len; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct omap2_mcspi_device_config { 18*4882a593Smuzhiyun unsigned turbo_mode:1; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* toggle chip select after every word */ 21*4882a593Smuzhiyun unsigned cs_per_word:1; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif 25