1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2009 Texas Instruments. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ARCH_ARM_DAVINCI_SPI_H 7*4882a593Smuzhiyun #define __ARCH_ARM_DAVINCI_SPI_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/platform_data/edma.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SPI_INTERN_CS 0xFF 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun enum { 14*4882a593Smuzhiyun SPI_VERSION_1, /* For DM355/DM365/DM6467 */ 15*4882a593Smuzhiyun SPI_VERSION_2, /* For DA8xx */ 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /** 19*4882a593Smuzhiyun * davinci_spi_platform_data - Platform data for SPI master device on DaVinci 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * @version: version of the SPI IP. Different DaVinci devices have slightly 22*4882a593Smuzhiyun * varying versions of the same IP. 23*4882a593Smuzhiyun * @num_chipselect: number of chipselects supported by this SPI master 24*4882a593Smuzhiyun * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt 25*4882a593Smuzhiyun * controller withn the SoC. Possible values are 0 and 1. 26*4882a593Smuzhiyun * @cshold_bug: set this to true if the SPI controller on your chip requires 27*4882a593Smuzhiyun * a write to CSHOLD bit in between transfers (like in DM355). 28*4882a593Smuzhiyun * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any 29*4882a593Smuzhiyun * device on the bus. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun struct davinci_spi_platform_data { 32*4882a593Smuzhiyun u8 version; 33*4882a593Smuzhiyun u8 num_chipselect; 34*4882a593Smuzhiyun u8 intr_line; 35*4882a593Smuzhiyun u8 prescaler_limit; 36*4882a593Smuzhiyun bool cshold_bug; 37*4882a593Smuzhiyun enum dma_event_q dma_event_q; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /** 41*4882a593Smuzhiyun * davinci_spi_config - Per-chip-select configuration for SPI slave devices 42*4882a593Smuzhiyun * 43*4882a593Smuzhiyun * @wdelay: amount of delay between transmissions. Measured in number of 44*4882a593Smuzhiyun * SPI module clocks. 45*4882a593Smuzhiyun * @odd_parity: polarity of parity flag at the end of transmit data stream. 46*4882a593Smuzhiyun * 0 - odd parity, 1 - even parity. 47*4882a593Smuzhiyun * @parity_enable: enable transmission of parity at end of each transmit 48*4882a593Smuzhiyun * data stream. 49*4882a593Smuzhiyun * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. 50*4882a593Smuzhiyun * @timer_disable: disable chip-select timers (setup and hold) 51*4882a593Smuzhiyun * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. 52*4882a593Smuzhiyun * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. 53*4882a593Smuzhiyun * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured 54*4882a593Smuzhiyun * in number of SPI clocks. 55*4882a593Smuzhiyun * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in 56*4882a593Smuzhiyun * number of SPI clocks. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun struct davinci_spi_config { 59*4882a593Smuzhiyun u8 wdelay; 60*4882a593Smuzhiyun u8 odd_parity; 61*4882a593Smuzhiyun u8 parity_enable; 62*4882a593Smuzhiyun #define SPI_IO_TYPE_INTR 0 63*4882a593Smuzhiyun #define SPI_IO_TYPE_POLL 1 64*4882a593Smuzhiyun #define SPI_IO_TYPE_DMA 2 65*4882a593Smuzhiyun u8 io_type; 66*4882a593Smuzhiyun u8 timer_disable; 67*4882a593Smuzhiyun u8 c2tdelay; 68*4882a593Smuzhiyun u8 t2cdelay; 69*4882a593Smuzhiyun u8 t2edelay; 70*4882a593Smuzhiyun u8 c2edelay; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* __ARCH_ARM_DAVINCI_SPI_H */ 74