1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Si5351A/B/C programmable clock generator platform_data. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __LINUX_PLATFORM_DATA_SI5351_H__ 7*4882a593Smuzhiyun #define __LINUX_PLATFORM_DATA_SI5351_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /** 10*4882a593Smuzhiyun * enum si5351_pll_src - Si5351 pll clock source 11*4882a593Smuzhiyun * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config 12*4882a593Smuzhiyun * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input 13*4882a593Smuzhiyun * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only) 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun enum si5351_pll_src { 16*4882a593Smuzhiyun SI5351_PLL_SRC_DEFAULT = 0, 17*4882a593Smuzhiyun SI5351_PLL_SRC_XTAL = 1, 18*4882a593Smuzhiyun SI5351_PLL_SRC_CLKIN = 2, 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /** 22*4882a593Smuzhiyun * enum si5351_multisynth_src - Si5351 multisynth clock source 23*4882a593Smuzhiyun * @SI5351_MULTISYNTH_SRC_DEFAULT: default, do not change eeprom config 24*4882a593Smuzhiyun * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0 25*4882a593Smuzhiyun * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun enum si5351_multisynth_src { 28*4882a593Smuzhiyun SI5351_MULTISYNTH_SRC_DEFAULT = 0, 29*4882a593Smuzhiyun SI5351_MULTISYNTH_SRC_VCO0 = 1, 30*4882a593Smuzhiyun SI5351_MULTISYNTH_SRC_VCO1 = 2, 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /** 34*4882a593Smuzhiyun * enum si5351_clkout_src - Si5351 clock output clock source 35*4882a593Smuzhiyun * @SI5351_CLKOUT_SRC_DEFAULT: default, do not change eeprom config 36*4882a593Smuzhiyun * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N 37*4882a593Smuzhiyun * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4) 38*4882a593Smuzhiyun * or 4 (N>=4) 39*4882a593Smuzhiyun * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL 40*4882a593Smuzhiyun * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only) 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun enum si5351_clkout_src { 43*4882a593Smuzhiyun SI5351_CLKOUT_SRC_DEFAULT = 0, 44*4882a593Smuzhiyun SI5351_CLKOUT_SRC_MSYNTH_N = 1, 45*4882a593Smuzhiyun SI5351_CLKOUT_SRC_MSYNTH_0_4 = 2, 46*4882a593Smuzhiyun SI5351_CLKOUT_SRC_XTAL = 3, 47*4882a593Smuzhiyun SI5351_CLKOUT_SRC_CLKIN = 4, 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /** 51*4882a593Smuzhiyun * enum si5351_drive_strength - Si5351 clock output drive strength 52*4882a593Smuzhiyun * @SI5351_DRIVE_DEFAULT: default, do not change eeprom config 53*4882a593Smuzhiyun * @SI5351_DRIVE_2MA: 2mA clock output drive strength 54*4882a593Smuzhiyun * @SI5351_DRIVE_4MA: 4mA clock output drive strength 55*4882a593Smuzhiyun * @SI5351_DRIVE_6MA: 6mA clock output drive strength 56*4882a593Smuzhiyun * @SI5351_DRIVE_8MA: 8mA clock output drive strength 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun enum si5351_drive_strength { 59*4882a593Smuzhiyun SI5351_DRIVE_DEFAULT = 0, 60*4882a593Smuzhiyun SI5351_DRIVE_2MA = 2, 61*4882a593Smuzhiyun SI5351_DRIVE_4MA = 4, 62*4882a593Smuzhiyun SI5351_DRIVE_6MA = 6, 63*4882a593Smuzhiyun SI5351_DRIVE_8MA = 8, 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /** 67*4882a593Smuzhiyun * enum si5351_disable_state - Si5351 clock output disable state 68*4882a593Smuzhiyun * @SI5351_DISABLE_DEFAULT: default, do not change eeprom config 69*4882a593Smuzhiyun * @SI5351_DISABLE_LOW: CLKx is set to a LOW state when disabled 70*4882a593Smuzhiyun * @SI5351_DISABLE_HIGH: CLKx is set to a HIGH state when disabled 71*4882a593Smuzhiyun * @SI5351_DISABLE_FLOATING: CLKx is set to a FLOATING state when 72*4882a593Smuzhiyun * disabled 73*4882a593Smuzhiyun * @SI5351_DISABLE_NEVER: CLKx is NEVER disabled 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun enum si5351_disable_state { 76*4882a593Smuzhiyun SI5351_DISABLE_DEFAULT = 0, 77*4882a593Smuzhiyun SI5351_DISABLE_LOW, 78*4882a593Smuzhiyun SI5351_DISABLE_HIGH, 79*4882a593Smuzhiyun SI5351_DISABLE_FLOATING, 80*4882a593Smuzhiyun SI5351_DISABLE_NEVER, 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /** 84*4882a593Smuzhiyun * struct si5351_clkout_config - Si5351 clock output configuration 85*4882a593Smuzhiyun * @clkout: clkout number 86*4882a593Smuzhiyun * @multisynth_src: multisynth source clock 87*4882a593Smuzhiyun * @clkout_src: clkout source clock 88*4882a593Smuzhiyun * @pll_master: if true, clkout can also change pll rate 89*4882a593Smuzhiyun * @pll_reset: if true, clkout can reset its pll 90*4882a593Smuzhiyun * @drive: output drive strength 91*4882a593Smuzhiyun * @rate: initial clkout rate, or default if 0 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun struct si5351_clkout_config { 94*4882a593Smuzhiyun enum si5351_multisynth_src multisynth_src; 95*4882a593Smuzhiyun enum si5351_clkout_src clkout_src; 96*4882a593Smuzhiyun enum si5351_drive_strength drive; 97*4882a593Smuzhiyun enum si5351_disable_state disable_state; 98*4882a593Smuzhiyun bool pll_master; 99*4882a593Smuzhiyun bool pll_reset; 100*4882a593Smuzhiyun unsigned long rate; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /** 104*4882a593Smuzhiyun * struct si5351_platform_data - Platform data for the Si5351 clock driver 105*4882a593Smuzhiyun * @clk_xtal: xtal input clock 106*4882a593Smuzhiyun * @clk_clkin: clkin input clock 107*4882a593Smuzhiyun * @pll_src: array of pll source clock setting 108*4882a593Smuzhiyun * @clkout: array of clkout configuration 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun struct si5351_platform_data { 111*4882a593Smuzhiyun enum si5351_pll_src pll_src[2]; 112*4882a593Smuzhiyun struct si5351_clkout_config clkout[8]; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #endif 116