1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * NXP (Philips) SCC+++(SCN+++) serial driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _PLATFORM_DATA_SERIAL_SCCNXP_H_ 11*4882a593Smuzhiyun #define _PLATFORM_DATA_SERIAL_SCCNXP_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define SCCNXP_MAX_UARTS 2 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Output lines */ 16*4882a593Smuzhiyun #define LINE_OP0 1 17*4882a593Smuzhiyun #define LINE_OP1 2 18*4882a593Smuzhiyun #define LINE_OP2 3 19*4882a593Smuzhiyun #define LINE_OP3 4 20*4882a593Smuzhiyun #define LINE_OP4 5 21*4882a593Smuzhiyun #define LINE_OP5 6 22*4882a593Smuzhiyun #define LINE_OP6 7 23*4882a593Smuzhiyun #define LINE_OP7 8 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Input lines */ 26*4882a593Smuzhiyun #define LINE_IP0 9 27*4882a593Smuzhiyun #define LINE_IP1 10 28*4882a593Smuzhiyun #define LINE_IP2 11 29*4882a593Smuzhiyun #define LINE_IP3 12 30*4882a593Smuzhiyun #define LINE_IP4 13 31*4882a593Smuzhiyun #define LINE_IP5 14 32*4882a593Smuzhiyun #define LINE_IP6 15 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Signals */ 35*4882a593Smuzhiyun #define DTR_OP 0 /* DTR */ 36*4882a593Smuzhiyun #define RTS_OP 4 /* RTS */ 37*4882a593Smuzhiyun #define DSR_IP 8 /* DSR */ 38*4882a593Smuzhiyun #define CTS_IP 12 /* CTS */ 39*4882a593Smuzhiyun #define DCD_IP 16 /* DCD */ 40*4882a593Smuzhiyun #define RNG_IP 20 /* RNG */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define DIR_OP 24 /* Special signal for control RS-485. 43*4882a593Smuzhiyun * Goes high when transmit, 44*4882a593Smuzhiyun * then goes low. 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Routing control signal 'sig' to line 'line' */ 48*4882a593Smuzhiyun #define MCTRL_SIG(sig, line) ((line) << (sig)) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * Example board initialization data: 52*4882a593Smuzhiyun * 53*4882a593Smuzhiyun * static struct resource sc2892_resources[] = { 54*4882a593Smuzhiyun * DEFINE_RES_MEM(UART_PHYS_START, 0x10), 55*4882a593Smuzhiyun * DEFINE_RES_IRQ(IRQ_EXT2), 56*4882a593Smuzhiyun * }; 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun * static struct sccnxp_pdata sc2892_info = { 59*4882a593Smuzhiyun * .mctrl_cfg[0] = MCTRL_SIG(DIR_OP, LINE_OP0), 60*4882a593Smuzhiyun * .mctrl_cfg[1] = MCTRL_SIG(DIR_OP, LINE_OP1), 61*4882a593Smuzhiyun * }; 62*4882a593Smuzhiyun * 63*4882a593Smuzhiyun * static struct platform_device sc2892 = { 64*4882a593Smuzhiyun * .name = "sc2892", 65*4882a593Smuzhiyun * .id = -1, 66*4882a593Smuzhiyun * .resource = sc2892_resources, 67*4882a593Smuzhiyun * .num_resources = ARRAY_SIZE(sc2892_resources), 68*4882a593Smuzhiyun * .dev = { 69*4882a593Smuzhiyun * .platform_data = &sc2892_info, 70*4882a593Smuzhiyun * }, 71*4882a593Smuzhiyun * }; 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* SCCNXP platform data structure */ 75*4882a593Smuzhiyun struct sccnxp_pdata { 76*4882a593Smuzhiyun /* Shift for A0 line */ 77*4882a593Smuzhiyun const u8 reg_shift; 78*4882a593Smuzhiyun /* Modem control lines configuration */ 79*4882a593Smuzhiyun const u32 mctrl_cfg[SCCNXP_MAX_UARTS]; 80*4882a593Smuzhiyun /* Timer value for polling mode (usecs) */ 81*4882a593Smuzhiyun const unsigned int poll_time_us; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif 85