1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/linux/platform_data/pxa_sdhci.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010 Marvell 6*4882a593Smuzhiyun * Zhangfei Gao <zhangfei.gao@marvell.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * PXA Platform - SDHCI platform data definitions 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _PXA_SDHCI_H_ 12*4882a593Smuzhiyun #define _PXA_SDHCI_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* pxa specific flag */ 15*4882a593Smuzhiyun /* Require clock free running */ 16*4882a593Smuzhiyun #define PXA_FLAG_ENABLE_CLOCK_GATING (1<<0) 17*4882a593Smuzhiyun /* card always wired to host, like on-chip emmc */ 18*4882a593Smuzhiyun #define PXA_FLAG_CARD_PERMANENT (1<<1) 19*4882a593Smuzhiyun /* Board design supports 8-bit data on SD/SDIO BUS */ 20*4882a593Smuzhiyun #define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI 24*4882a593Smuzhiyun * @flags: flags for platform requirement 25*4882a593Smuzhiyun * @clk_delay_cycles: 26*4882a593Smuzhiyun * mmp2: each step is roughly 100ps, 5bits width 27*4882a593Smuzhiyun * pxa910: each step is 1ns, 4bits width 28*4882a593Smuzhiyun * @clk_delay_sel: select clk_delay, used on pxa910 29*4882a593Smuzhiyun * 0: choose feedback clk 30*4882a593Smuzhiyun * 1: choose feedback clk + delay value 31*4882a593Smuzhiyun * 2: choose internal clk 32*4882a593Smuzhiyun * @clk_delay_enable: enable clk_delay or not, used on pxa910 33*4882a593Smuzhiyun * @max_speed: the maximum speed supported 34*4882a593Smuzhiyun * @host_caps: Standard MMC host capabilities bit field. 35*4882a593Smuzhiyun * @quirks: quirks of platfrom 36*4882a593Smuzhiyun * @quirks2: quirks2 of platfrom 37*4882a593Smuzhiyun * @pm_caps: pm_caps of platfrom 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun struct sdhci_pxa_platdata { 40*4882a593Smuzhiyun unsigned int flags; 41*4882a593Smuzhiyun unsigned int clk_delay_cycles; 42*4882a593Smuzhiyun unsigned int clk_delay_sel; 43*4882a593Smuzhiyun bool clk_delay_enable; 44*4882a593Smuzhiyun unsigned int max_speed; 45*4882a593Smuzhiyun u32 host_caps; 46*4882a593Smuzhiyun u32 host_caps2; 47*4882a593Smuzhiyun unsigned int quirks; 48*4882a593Smuzhiyun unsigned int quirks2; 49*4882a593Smuzhiyun unsigned int pm_caps; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun #endif /* _PXA_SDHCI_H_ */ 52