1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2006 Micron Technology Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _MTD_NAND_OMAP2_H 7*4882a593Smuzhiyun #define _MTD_NAND_OMAP2_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/mtd/partitions.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define GPMC_BCH_NUM_REMAINDER 8 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun enum nand_io { 14*4882a593Smuzhiyun NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */ 15*4882a593Smuzhiyun NAND_OMAP_POLLED, /* polled mode, without prefetch */ 16*4882a593Smuzhiyun NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */ 17*4882a593Smuzhiyun NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */ 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum omap_ecc { 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * 1-bit ECC: calculation and correction by SW 23*4882a593Smuzhiyun * ECC stored at end of spare area 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun OMAP_ECC_HAM1_CODE_SW = 0, 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * 1-bit ECC: calculation by GPMC, Error detection by Software 29*4882a593Smuzhiyun * ECC layout compatible with ROM code layout 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun OMAP_ECC_HAM1_CODE_HW, 32*4882a593Smuzhiyun /* 4-bit ECC calculation by GPMC, Error detection by Software */ 33*4882a593Smuzhiyun OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, 34*4882a593Smuzhiyun /* 4-bit ECC calculation by GPMC, Error detection by ELM */ 35*4882a593Smuzhiyun OMAP_ECC_BCH4_CODE_HW, 36*4882a593Smuzhiyun /* 8-bit ECC calculation by GPMC, Error detection by Software */ 37*4882a593Smuzhiyun OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, 38*4882a593Smuzhiyun /* 8-bit ECC calculation by GPMC, Error detection by ELM */ 39*4882a593Smuzhiyun OMAP_ECC_BCH8_CODE_HW, 40*4882a593Smuzhiyun /* 16-bit ECC calculation by GPMC, Error detection by ELM */ 41*4882a593Smuzhiyun OMAP_ECC_BCH16_CODE_HW, 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct gpmc_nand_regs { 45*4882a593Smuzhiyun void __iomem *gpmc_nand_command; 46*4882a593Smuzhiyun void __iomem *gpmc_nand_address; 47*4882a593Smuzhiyun void __iomem *gpmc_nand_data; 48*4882a593Smuzhiyun void __iomem *gpmc_prefetch_config1; 49*4882a593Smuzhiyun void __iomem *gpmc_prefetch_config2; 50*4882a593Smuzhiyun void __iomem *gpmc_prefetch_control; 51*4882a593Smuzhiyun void __iomem *gpmc_prefetch_status; 52*4882a593Smuzhiyun void __iomem *gpmc_ecc_config; 53*4882a593Smuzhiyun void __iomem *gpmc_ecc_control; 54*4882a593Smuzhiyun void __iomem *gpmc_ecc_size_config; 55*4882a593Smuzhiyun void __iomem *gpmc_ecc1_result; 56*4882a593Smuzhiyun void __iomem *gpmc_bch_result0[GPMC_BCH_NUM_REMAINDER]; 57*4882a593Smuzhiyun void __iomem *gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER]; 58*4882a593Smuzhiyun void __iomem *gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER]; 59*4882a593Smuzhiyun void __iomem *gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER]; 60*4882a593Smuzhiyun void __iomem *gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER]; 61*4882a593Smuzhiyun void __iomem *gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER]; 62*4882a593Smuzhiyun void __iomem *gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER]; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun #endif 65