1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mach-davinci/nand.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright © 2006 Texas Instruments. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Ported to 2.6.23 Copyright © 2008 by 8*4882a593Smuzhiyun * Sander Huijsen <Shuijsen@optelecom-nkf.com> 9*4882a593Smuzhiyun * Troy Kisky <troy.kisky@boundarydevices.com> 10*4882a593Smuzhiyun * Dirk Behme <Dirk.Behme@gmail.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * -------------------------------------------------------------------------- 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __ARCH_ARM_DAVINCI_NAND_H 16*4882a593Smuzhiyun #define __ARCH_ARM_DAVINCI_NAND_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <linux/mtd/rawnand.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define NANDFCR_OFFSET 0x60 21*4882a593Smuzhiyun #define NANDFSR_OFFSET 0x64 22*4882a593Smuzhiyun #define NANDF1ECC_OFFSET 0x70 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 4-bit ECC syndrome registers */ 25*4882a593Smuzhiyun #define NAND_4BIT_ECC_LOAD_OFFSET 0xbc 26*4882a593Smuzhiyun #define NAND_4BIT_ECC1_OFFSET 0xc0 27*4882a593Smuzhiyun #define NAND_4BIT_ECC2_OFFSET 0xc4 28*4882a593Smuzhiyun #define NAND_4BIT_ECC3_OFFSET 0xc8 29*4882a593Smuzhiyun #define NAND_4BIT_ECC4_OFFSET 0xcc 30*4882a593Smuzhiyun #define NAND_ERR_ADD1_OFFSET 0xd0 31*4882a593Smuzhiyun #define NAND_ERR_ADD2_OFFSET 0xd4 32*4882a593Smuzhiyun #define NAND_ERR_ERRVAL1_OFFSET 0xd8 33*4882a593Smuzhiyun #define NAND_ERR_ERRVAL2_OFFSET 0xdc 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* NOTE: boards don't need to use these address bits 36*4882a593Smuzhiyun * for ALE/CLE unless they support booting from NAND. 37*4882a593Smuzhiyun * They're used unless platform data overrides them. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #define MASK_ALE 0x08 40*4882a593Smuzhiyun #define MASK_CLE 0x10 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct davinci_nand_pdata { /* platform_data */ 43*4882a593Smuzhiyun uint32_t mask_ale; 44*4882a593Smuzhiyun uint32_t mask_cle; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * 0-indexed chip-select number of the asynchronous 48*4882a593Smuzhiyun * interface to which the NAND device has been connected. 49*4882a593Smuzhiyun * 50*4882a593Smuzhiyun * So, if you have NAND connected to CS3 of DA850, you 51*4882a593Smuzhiyun * will pass '1' here. Since the asynchronous interface 52*4882a593Smuzhiyun * on DA850 starts from CS2. 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun uint32_t core_chipsel; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* for packages using two chipselects */ 57*4882a593Smuzhiyun uint32_t mask_chipsel; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* board's default static partition info */ 60*4882a593Smuzhiyun struct mtd_partition *parts; 61*4882a593Smuzhiyun unsigned nr_parts; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* none == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) 64*4882a593Smuzhiyun * soft == NAND_ECC_ENGINE_TYPE_SOFT 65*4882a593Smuzhiyun * else == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * All DaVinci-family chips support 1-bit hardware ECC. 68*4882a593Smuzhiyun * Newer ones also support 4-bit ECC, but are awkward 69*4882a593Smuzhiyun * using it with large page chips. 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun enum nand_ecc_engine_type engine_type; 72*4882a593Smuzhiyun enum nand_ecc_placement ecc_placement; 73*4882a593Smuzhiyun u8 ecc_bits; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* e.g. NAND_BUSWIDTH_16 */ 76*4882a593Smuzhiyun unsigned options; 77*4882a593Smuzhiyun /* e.g. NAND_BBT_USE_FLASH */ 78*4882a593Smuzhiyun unsigned bbt_options; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Main and mirror bbt descriptor overrides */ 81*4882a593Smuzhiyun struct nand_bbt_descr *bbt_td; 82*4882a593Smuzhiyun struct nand_bbt_descr *bbt_md; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Access timings */ 85*4882a593Smuzhiyun struct davinci_aemif_timing *timing; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* __ARCH_ARM_DAVINCI_NAND_H */ 89