1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Information for the Marvell Armada MMP camera 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include <media/v4l2-mediabus.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun enum dphy3_algo { 9*4882a593Smuzhiyun DPHY3_ALGO_DEFAULT = 0, 10*4882a593Smuzhiyun DPHY3_ALGO_PXA910, 11*4882a593Smuzhiyun DPHY3_ALGO_PXA2128 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct mmp_camera_platform_data { 15*4882a593Smuzhiyun enum v4l2_mbus_type bus_type; 16*4882a593Smuzhiyun int mclk_src; /* which clock source the MCLK derives from */ 17*4882a593Smuzhiyun int mclk_div; /* Clock Divider Value for MCLK */ 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * MIPI support 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun int dphy[3]; /* DPHY: CSI2_DPHY3, CSI2_DPHY5, CSI2_DPHY6 */ 22*4882a593Smuzhiyun enum dphy3_algo dphy3_algo; /* algos for calculate CSI2_DPHY3 */ 23*4882a593Smuzhiyun int lane; /* ccic used lane number; 0 means DVP mode */ 24*4882a593Smuzhiyun int lane_clk; 25*4882a593Smuzhiyun }; 26