1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _GSC_HWMON_H 3*4882a593Smuzhiyun #define _GSC_HWMON_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun enum gsc_hwmon_mode { 6*4882a593Smuzhiyun mode_temperature, 7*4882a593Smuzhiyun mode_voltage_24bit, 8*4882a593Smuzhiyun mode_voltage_raw, 9*4882a593Smuzhiyun mode_voltage_16bit, 10*4882a593Smuzhiyun mode_fan, 11*4882a593Smuzhiyun mode_max, 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /** 15*4882a593Smuzhiyun * struct gsc_hwmon_channel - configuration parameters 16*4882a593Smuzhiyun * @reg: I2C register offset 17*4882a593Smuzhiyun * @mode: channel mode 18*4882a593Smuzhiyun * @name: channel name 19*4882a593Smuzhiyun * @mvoffset: voltage offset 20*4882a593Smuzhiyun * @vdiv: voltage divider array (2 resistor values in milli-ohms) 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun struct gsc_hwmon_channel { 23*4882a593Smuzhiyun unsigned int reg; 24*4882a593Smuzhiyun unsigned int mode; 25*4882a593Smuzhiyun const char *name; 26*4882a593Smuzhiyun unsigned int mvoffset; 27*4882a593Smuzhiyun unsigned int vdiv[2]; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /** 31*4882a593Smuzhiyun * struct gsc_hwmon_platform_data - platform data for gsc_hwmon driver 32*4882a593Smuzhiyun * @channels: pointer to array of gsc_hwmon_channel structures 33*4882a593Smuzhiyun * describing channels 34*4882a593Smuzhiyun * @nchannels: number of elements in @channels array 35*4882a593Smuzhiyun * @vreference: voltage reference (mV) 36*4882a593Smuzhiyun * @resolution: ADC bit resolution 37*4882a593Smuzhiyun * @fan_base: register base for FAN controller 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun struct gsc_hwmon_platform_data { 40*4882a593Smuzhiyun const struct gsc_hwmon_channel *channels; 41*4882a593Smuzhiyun int nchannels; 42*4882a593Smuzhiyun unsigned int resolution; 43*4882a593Smuzhiyun unsigned int vreference; 44*4882a593Smuzhiyun unsigned int fan_base; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun #endif 47