1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright(c) 2014 Intel Corporation. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef GPIO_DW_APB_H 7*4882a593Smuzhiyun #define GPIO_DW_APB_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define DWAPB_MAX_GPIOS 32 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct dwapb_port_property { 12*4882a593Smuzhiyun struct fwnode_handle *fwnode; 13*4882a593Smuzhiyun unsigned int idx; 14*4882a593Smuzhiyun unsigned int ngpio; 15*4882a593Smuzhiyun unsigned int gpio_base; 16*4882a593Smuzhiyun int irq[DWAPB_MAX_GPIOS]; 17*4882a593Smuzhiyun bool irq_shared; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct dwapb_platform_data { 21*4882a593Smuzhiyun struct dwapb_port_property *properties; 22*4882a593Smuzhiyun unsigned int nports; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif 26