1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Inspired by pxafb.h 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_PLAT_FB_S3C2410_H 9*4882a593Smuzhiyun #define __ASM_PLAT_FB_S3C2410_H __FILE__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/compiler_types.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct s3c2410fb_hw { 14*4882a593Smuzhiyun unsigned long lcdcon1; 15*4882a593Smuzhiyun unsigned long lcdcon2; 16*4882a593Smuzhiyun unsigned long lcdcon3; 17*4882a593Smuzhiyun unsigned long lcdcon4; 18*4882a593Smuzhiyun unsigned long lcdcon5; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* LCD description */ 22*4882a593Smuzhiyun struct s3c2410fb_display { 23*4882a593Smuzhiyun /* LCD type */ 24*4882a593Smuzhiyun unsigned type; 25*4882a593Smuzhiyun #define S3C2410_LCDCON1_DSCAN4 (0<<5) 26*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN4 (1<<5) 27*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN8 (2<<5) 28*4882a593Smuzhiyun #define S3C2410_LCDCON1_TFT (3<<5) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define S3C2410_LCDCON1_TFT1BPP (8<<1) 31*4882a593Smuzhiyun #define S3C2410_LCDCON1_TFT2BPP (9<<1) 32*4882a593Smuzhiyun #define S3C2410_LCDCON1_TFT4BPP (10<<1) 33*4882a593Smuzhiyun #define S3C2410_LCDCON1_TFT8BPP (11<<1) 34*4882a593Smuzhiyun #define S3C2410_LCDCON1_TFT16BPP (12<<1) 35*4882a593Smuzhiyun #define S3C2410_LCDCON1_TFT24BPP (13<<1) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Screen size */ 38*4882a593Smuzhiyun unsigned short width; 39*4882a593Smuzhiyun unsigned short height; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Screen info */ 42*4882a593Smuzhiyun unsigned short xres; 43*4882a593Smuzhiyun unsigned short yres; 44*4882a593Smuzhiyun unsigned short bpp; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun unsigned pixclock; /* pixclock in picoseconds */ 47*4882a593Smuzhiyun unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */ 48*4882a593Smuzhiyun unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */ 49*4882a593Smuzhiyun unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */ 50*4882a593Smuzhiyun unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */ 51*4882a593Smuzhiyun unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */ 52*4882a593Smuzhiyun unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* lcd configuration registers */ 55*4882a593Smuzhiyun unsigned long lcdcon5; 56*4882a593Smuzhiyun #define S3C2410_LCDCON5_BPP24BL (1<<12) 57*4882a593Smuzhiyun #define S3C2410_LCDCON5_FRM565 (1<<11) 58*4882a593Smuzhiyun #define S3C2410_LCDCON5_INVVCLK (1<<10) 59*4882a593Smuzhiyun #define S3C2410_LCDCON5_INVVLINE (1<<9) 60*4882a593Smuzhiyun #define S3C2410_LCDCON5_INVVFRAME (1<<8) 61*4882a593Smuzhiyun #define S3C2410_LCDCON5_INVVD (1<<7) 62*4882a593Smuzhiyun #define S3C2410_LCDCON5_INVVDEN (1<<6) 63*4882a593Smuzhiyun #define S3C2410_LCDCON5_INVPWREN (1<<5) 64*4882a593Smuzhiyun #define S3C2410_LCDCON5_INVLEND (1<<4) 65*4882a593Smuzhiyun #define S3C2410_LCDCON5_PWREN (1<<3) 66*4882a593Smuzhiyun #define S3C2410_LCDCON5_ENLEND (1<<2) 67*4882a593Smuzhiyun #define S3C2410_LCDCON5_BSWP (1<<1) 68*4882a593Smuzhiyun #define S3C2410_LCDCON5_HWSWP (1<<0) 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct s3c2410fb_mach_info { 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct s3c2410fb_display *displays; /* attached displays info */ 74*4882a593Smuzhiyun unsigned num_displays; /* number of defined displays */ 75*4882a593Smuzhiyun unsigned default_display; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* GPIOs */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun unsigned long gpcup; 80*4882a593Smuzhiyun unsigned long gpcup_mask; 81*4882a593Smuzhiyun unsigned long gpccon; 82*4882a593Smuzhiyun unsigned long gpccon_mask; 83*4882a593Smuzhiyun unsigned long gpdup; 84*4882a593Smuzhiyun unsigned long gpdup_mask; 85*4882a593Smuzhiyun unsigned long gpdcon; 86*4882a593Smuzhiyun unsigned long gpdcon_mask; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun void __iomem * gpccon_reg; 89*4882a593Smuzhiyun void __iomem * gpcup_reg; 90*4882a593Smuzhiyun void __iomem * gpdcon_reg; 91*4882a593Smuzhiyun void __iomem * gpdup_reg; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* lpc3600 control register */ 94*4882a593Smuzhiyun unsigned long lpcsel; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun extern void s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *); 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif /* __ASM_PLAT_FB_S3C2410_H */ 100