1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Definitions for TI EMIF device platform data 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __EMIF_PLAT_H 10*4882a593Smuzhiyun #define __EMIF_PLAT_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Low power modes - EMIF_PWR_MGMT_CTRL */ 13*4882a593Smuzhiyun #define EMIF_LP_MODE_DISABLE 0 14*4882a593Smuzhiyun #define EMIF_LP_MODE_CLOCK_STOP 1 15*4882a593Smuzhiyun #define EMIF_LP_MODE_SELF_REFRESH 2 16*4882a593Smuzhiyun #define EMIF_LP_MODE_PWR_DN 4 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Hardware capabilities */ 19*4882a593Smuzhiyun #define EMIF_HW_CAPS_LL_INTERFACE 0x00000001 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * EMIF IP Revisions 23*4882a593Smuzhiyun * EMIF4D - Used in OMAP4 24*4882a593Smuzhiyun * EMIF4D5 - Used in OMAP5 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define EMIF_4D 1 27*4882a593Smuzhiyun #define EMIF_4D5 2 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * PHY types 31*4882a593Smuzhiyun * ATTILAPHY - Used in OMAP4 32*4882a593Smuzhiyun * INTELLIPHY - Used in OMAP5 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define EMIF_PHY_TYPE_ATTILAPHY 1 35*4882a593Smuzhiyun #define EMIF_PHY_TYPE_INTELLIPHY 2 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Custom config requests */ 38*4882a593Smuzhiyun #define EMIF_CUSTOM_CONFIG_LPMODE 0x00000001 39*4882a593Smuzhiyun #define EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL 0x00000002 40*4882a593Smuzhiyun #define EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART 0x00000004 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 43*4882a593Smuzhiyun /** 44*4882a593Smuzhiyun * struct ddr_device_info - All information about the DDR device except AC 45*4882a593Smuzhiyun * timing parameters 46*4882a593Smuzhiyun * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc) 47*4882a593Smuzhiyun * @density: Device density 48*4882a593Smuzhiyun * @io_width: Bus width 49*4882a593Smuzhiyun * @cs1_used: Whether there is a DDR device attached to the second 50*4882a593Smuzhiyun * chip-select(CS1) of this EMIF instance 51*4882a593Smuzhiyun * @cal_resistors_per_cs: Whether there is one calibration resistor per 52*4882a593Smuzhiyun * chip-select or whether it's a single one for both 53*4882a593Smuzhiyun * @manufacturer: Manufacturer name string 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun struct ddr_device_info { 56*4882a593Smuzhiyun u32 type; 57*4882a593Smuzhiyun u32 density; 58*4882a593Smuzhiyun u32 io_width; 59*4882a593Smuzhiyun u32 cs1_used; 60*4882a593Smuzhiyun u32 cal_resistors_per_cs; 61*4882a593Smuzhiyun char manufacturer[10]; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /** 65*4882a593Smuzhiyun * struct emif_custom_configs - Custom configuration parameters/policies 66*4882a593Smuzhiyun * passed from the platform layer 67*4882a593Smuzhiyun * @mask: Mask to indicate which configs are requested 68*4882a593Smuzhiyun * @lpmode: LPMODE to be used in PWR_MGMT_CTRL register 69*4882a593Smuzhiyun * @lpmode_timeout_performance: Timeout before LPMODE entry when higher 70*4882a593Smuzhiyun * performance is desired at the cost of power (typically 71*4882a593Smuzhiyun * at higher OPPs) 72*4882a593Smuzhiyun * @lpmode_timeout_power: Timeout before LPMODE entry when better power 73*4882a593Smuzhiyun * savings is desired and performance is not important 74*4882a593Smuzhiyun * (typically at lower loads indicated by lower OPPs) 75*4882a593Smuzhiyun * @lpmode_freq_threshold: The DDR frequency threshold to identify between 76*4882a593Smuzhiyun * the above two cases: 77*4882a593Smuzhiyun * timeout = (freq >= lpmode_freq_threshold) ? 78*4882a593Smuzhiyun * lpmode_timeout_performance : 79*4882a593Smuzhiyun * lpmode_timeout_power; 80*4882a593Smuzhiyun * @temp_alert_poll_interval_ms: LPDDR2 MR4 polling interval at nominal 81*4882a593Smuzhiyun * temperature(in milliseconds). When temperature is high 82*4882a593Smuzhiyun * polling is done 4 times as frequently. 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun struct emif_custom_configs { 85*4882a593Smuzhiyun u32 mask; 86*4882a593Smuzhiyun u32 lpmode; 87*4882a593Smuzhiyun u32 lpmode_timeout_performance; 88*4882a593Smuzhiyun u32 lpmode_timeout_power; 89*4882a593Smuzhiyun u32 lpmode_freq_threshold; 90*4882a593Smuzhiyun u32 temp_alert_poll_interval_ms; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /** 94*4882a593Smuzhiyun * struct emif_platform_data - Platform data passed on EMIF platform 95*4882a593Smuzhiyun * device creation. Used by the driver. 96*4882a593Smuzhiyun * @hw_caps: Hw capabilities of the EMIF IP in the respective SoC 97*4882a593Smuzhiyun * @device_info: Device info structure containing information such 98*4882a593Smuzhiyun * as type, bus width, density etc 99*4882a593Smuzhiyun * @timings: Timings information from device datasheet passed 100*4882a593Smuzhiyun * as an array of 'struct lpddr2_timings'. Can be NULL 101*4882a593Smuzhiyun * if if default timings are ok 102*4882a593Smuzhiyun * @timings_arr_size: Size of the timings array. Depends on the number 103*4882a593Smuzhiyun * of different frequencies for which timings data 104*4882a593Smuzhiyun * is provided 105*4882a593Smuzhiyun * @min_tck: Minimum value of some timing parameters in terms 106*4882a593Smuzhiyun * of number of cycles. Can be NULL if default values 107*4882a593Smuzhiyun * are ok 108*4882a593Smuzhiyun * @custom_configs: Custom configurations requested by SoC or board 109*4882a593Smuzhiyun * code and the data for them. Can be NULL if default 110*4882a593Smuzhiyun * configurations done by the driver are ok. See 111*4882a593Smuzhiyun * documentation for 'struct emif_custom_configs' for 112*4882a593Smuzhiyun * more details 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun struct emif_platform_data { 115*4882a593Smuzhiyun u32 hw_caps; 116*4882a593Smuzhiyun struct ddr_device_info *device_info; 117*4882a593Smuzhiyun const struct lpddr2_timings *timings; 118*4882a593Smuzhiyun u32 timings_arr_size; 119*4882a593Smuzhiyun const struct lpddr2_min_tck *min_tck; 120*4882a593Smuzhiyun struct emif_custom_configs *custom_configs; 121*4882a593Smuzhiyun u32 ip_rev; 122*4882a593Smuzhiyun u32 phy_type; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #endif /* __LINUX_EMIF_H */ 127