1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * TI EDMA definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2006-2013 Texas Instruments. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * This EDMA3 programming framework exposes two basic kinds of resource: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Channel Triggers transfers, usually from a hardware event but 12*4882a593Smuzhiyun * also manually or by "chaining" from DMA completions. 13*4882a593Smuzhiyun * Each channel is coupled to a Parameter RAM (PaRAM) slot. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM 16*4882a593Smuzhiyun * "set"), source and destination addresses, a link to a 17*4882a593Smuzhiyun * next PaRAM slot (if any), options for the transfer, and 18*4882a593Smuzhiyun * instructions for updating those addresses. There are 19*4882a593Smuzhiyun * more than twice as many slots as event channels. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * Each PaRAM set describes a sequence of transfers, either for one large 22*4882a593Smuzhiyun * buffer or for several discontiguous smaller buffers. An EDMA transfer 23*4882a593Smuzhiyun * is driven only from a channel, which performs the transfers specified 24*4882a593Smuzhiyun * in its PaRAM slot until there are no more transfers. When that last 25*4882a593Smuzhiyun * transfer completes, the "link" field may be used to reload the channel's 26*4882a593Smuzhiyun * PaRAM slot with a new transfer descriptor. 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * The EDMA Channel Controller (CC) maps requests from channels into physical 29*4882a593Smuzhiyun * Transfer Controller (TC) requests when the channel triggers (by hardware 30*4882a593Smuzhiyun * or software events, or by chaining). The two physical DMA channels provided 31*4882a593Smuzhiyun * by the TCs are thus shared by many logical channels. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * DaVinci hardware also has a "QDMA" mechanism which is not currently 34*4882a593Smuzhiyun * supported through this interface. (DSP firmware uses it though.) 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #ifndef EDMA_H_ 38*4882a593Smuzhiyun #define EDMA_H_ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun enum dma_event_q { 41*4882a593Smuzhiyun EVENTQ_0 = 0, 42*4882a593Smuzhiyun EVENTQ_1 = 1, 43*4882a593Smuzhiyun EVENTQ_2 = 2, 44*4882a593Smuzhiyun EVENTQ_3 = 3, 45*4882a593Smuzhiyun EVENTQ_DEFAULT = -1 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) 49*4882a593Smuzhiyun #define EDMA_CTLR(i) ((i) >> 16) 50*4882a593Smuzhiyun #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define EDMA_FILTER_PARAM(ctlr, chan) ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) }) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct edma_rsv_info { 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun const s16 (*rsv_chans)[2]; 57*4882a593Smuzhiyun const s16 (*rsv_slots)[2]; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct dma_slave_map; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* platform_data for EDMA driver */ 63*4882a593Smuzhiyun struct edma_soc_info { 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * Default queue is expected to be a low-priority queue. 66*4882a593Smuzhiyun * This way, long transfers on the default queue started 67*4882a593Smuzhiyun * by the codec engine will not cause audio defects. 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun enum dma_event_q default_queue; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Resource reservation for other cores */ 72*4882a593Smuzhiyun struct edma_rsv_info *rsv; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* List of channels allocated for memcpy, terminated with -1 */ 75*4882a593Smuzhiyun s32 *memcpy_channels; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun s8 (*queue_priority_mapping)[2]; 78*4882a593Smuzhiyun const s16 (*xbar_chans)[2]; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun const struct dma_slave_map *slave_map; 81*4882a593Smuzhiyun int slavecnt; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif 85