1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright © 2006, Intel Corporation. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef IOP_ADMA_H 6*4882a593Smuzhiyun #define IOP_ADMA_H 7*4882a593Smuzhiyun #include <linux/types.h> 8*4882a593Smuzhiyun #include <linux/dmaengine.h> 9*4882a593Smuzhiyun #include <linux/interrupt.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define IOP_ADMA_SLOT_SIZE 32 12*4882a593Smuzhiyun #define IOP_ADMA_THRESHOLD 4 13*4882a593Smuzhiyun #ifdef DEBUG 14*4882a593Smuzhiyun #define IOP_PARANOIA 1 15*4882a593Smuzhiyun #else 16*4882a593Smuzhiyun #define IOP_PARANOIA 0 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun #define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x)) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define DMA0_ID 0 21*4882a593Smuzhiyun #define DMA1_ID 1 22*4882a593Smuzhiyun #define AAU_ID 2 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /** 25*4882a593Smuzhiyun * struct iop_adma_device - internal representation of an ADMA device 26*4882a593Smuzhiyun * @pdev: Platform device 27*4882a593Smuzhiyun * @id: HW ADMA Device selector 28*4882a593Smuzhiyun * @dma_desc_pool: base of DMA descriptor region (DMA address) 29*4882a593Smuzhiyun * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) 30*4882a593Smuzhiyun * @common: embedded struct dma_device 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun struct iop_adma_device { 33*4882a593Smuzhiyun struct platform_device *pdev; 34*4882a593Smuzhiyun int id; 35*4882a593Smuzhiyun dma_addr_t dma_desc_pool; 36*4882a593Smuzhiyun void *dma_desc_pool_virt; 37*4882a593Smuzhiyun struct dma_device common; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /** 41*4882a593Smuzhiyun * struct iop_adma_chan - internal representation of an ADMA device 42*4882a593Smuzhiyun * @pending: allows batching of hardware operations 43*4882a593Smuzhiyun * @lock: serializes enqueue/dequeue operations to the slot pool 44*4882a593Smuzhiyun * @mmr_base: memory mapped register base 45*4882a593Smuzhiyun * @chain: device chain view of the descriptors 46*4882a593Smuzhiyun * @device: parent device 47*4882a593Smuzhiyun * @common: common dmaengine channel object members 48*4882a593Smuzhiyun * @last_used: place holder for allocation to continue from where it left off 49*4882a593Smuzhiyun * @all_slots: complete domain of slots usable by the channel 50*4882a593Smuzhiyun * @slots_allocated: records the actual size of the descriptor slot pool 51*4882a593Smuzhiyun * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun struct iop_adma_chan { 54*4882a593Smuzhiyun int pending; 55*4882a593Smuzhiyun spinlock_t lock; /* protects the descriptor slot pool */ 56*4882a593Smuzhiyun void __iomem *mmr_base; 57*4882a593Smuzhiyun struct list_head chain; 58*4882a593Smuzhiyun struct iop_adma_device *device; 59*4882a593Smuzhiyun struct dma_chan common; 60*4882a593Smuzhiyun struct iop_adma_desc_slot *last_used; 61*4882a593Smuzhiyun struct list_head all_slots; 62*4882a593Smuzhiyun int slots_allocated; 63*4882a593Smuzhiyun struct tasklet_struct irq_tasklet; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /** 67*4882a593Smuzhiyun * struct iop_adma_desc_slot - IOP-ADMA software descriptor 68*4882a593Smuzhiyun * @slot_node: node on the iop_adma_chan.all_slots list 69*4882a593Smuzhiyun * @chain_node: node on the op_adma_chan.chain list 70*4882a593Smuzhiyun * @hw_desc: virtual address of the hardware descriptor chain 71*4882a593Smuzhiyun * @phys: hardware address of the hardware descriptor chain 72*4882a593Smuzhiyun * @group_head: first operation in a transaction 73*4882a593Smuzhiyun * @slot_cnt: total slots used in an transaction (group of operations) 74*4882a593Smuzhiyun * @slots_per_op: number of slots per operation 75*4882a593Smuzhiyun * @idx: pool index 76*4882a593Smuzhiyun * @tx_list: list of descriptors that are associated with one operation 77*4882a593Smuzhiyun * @async_tx: support for the async_tx api 78*4882a593Smuzhiyun * @group_list: list of slots that make up a multi-descriptor transaction 79*4882a593Smuzhiyun * for example transfer lengths larger than the supported hw max 80*4882a593Smuzhiyun * @xor_check_result: result of zero sum 81*4882a593Smuzhiyun * @crc32_result: result crc calculation 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun struct iop_adma_desc_slot { 84*4882a593Smuzhiyun struct list_head slot_node; 85*4882a593Smuzhiyun struct list_head chain_node; 86*4882a593Smuzhiyun void *hw_desc; 87*4882a593Smuzhiyun struct iop_adma_desc_slot *group_head; 88*4882a593Smuzhiyun u16 slot_cnt; 89*4882a593Smuzhiyun u16 slots_per_op; 90*4882a593Smuzhiyun u16 idx; 91*4882a593Smuzhiyun struct list_head tx_list; 92*4882a593Smuzhiyun struct dma_async_tx_descriptor async_tx; 93*4882a593Smuzhiyun union { 94*4882a593Smuzhiyun u32 *xor_check_result; 95*4882a593Smuzhiyun u32 *crc32_result; 96*4882a593Smuzhiyun u32 *pq_check_result; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct iop_adma_platform_data { 101*4882a593Smuzhiyun int hw_id; 102*4882a593Smuzhiyun dma_cap_mask_t cap_mask; 103*4882a593Smuzhiyun size_t pool_size; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define to_iop_sw_desc(addr_hw_desc) \ 107*4882a593Smuzhiyun container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc) 108*4882a593Smuzhiyun #define iop_hw_desc_slot_idx(hw_desc, idx) \ 109*4882a593Smuzhiyun ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) ) 110*4882a593Smuzhiyun #endif 111