1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __MACH_MXC_SDMA_H__ 3*4882a593Smuzhiyun #define __MACH_MXC_SDMA_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /** 6*4882a593Smuzhiyun * struct sdma_script_start_addrs - SDMA script start pointers 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * start addresses of the different functions in the physical 9*4882a593Smuzhiyun * address space of the SDMA engine. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun struct sdma_script_start_addrs { 12*4882a593Smuzhiyun s32 ap_2_ap_addr; 13*4882a593Smuzhiyun s32 ap_2_bp_addr; 14*4882a593Smuzhiyun s32 ap_2_ap_fixed_addr; 15*4882a593Smuzhiyun s32 bp_2_ap_addr; 16*4882a593Smuzhiyun s32 loopback_on_dsp_side_addr; 17*4882a593Smuzhiyun s32 mcu_interrupt_only_addr; 18*4882a593Smuzhiyun s32 firi_2_per_addr; 19*4882a593Smuzhiyun s32 firi_2_mcu_addr; 20*4882a593Smuzhiyun s32 per_2_firi_addr; 21*4882a593Smuzhiyun s32 mcu_2_firi_addr; 22*4882a593Smuzhiyun s32 uart_2_per_addr; 23*4882a593Smuzhiyun s32 uart_2_mcu_addr; 24*4882a593Smuzhiyun s32 per_2_app_addr; 25*4882a593Smuzhiyun s32 mcu_2_app_addr; 26*4882a593Smuzhiyun s32 per_2_per_addr; 27*4882a593Smuzhiyun s32 uartsh_2_per_addr; 28*4882a593Smuzhiyun s32 uartsh_2_mcu_addr; 29*4882a593Smuzhiyun s32 per_2_shp_addr; 30*4882a593Smuzhiyun s32 mcu_2_shp_addr; 31*4882a593Smuzhiyun s32 ata_2_mcu_addr; 32*4882a593Smuzhiyun s32 mcu_2_ata_addr; 33*4882a593Smuzhiyun s32 app_2_per_addr; 34*4882a593Smuzhiyun s32 app_2_mcu_addr; 35*4882a593Smuzhiyun s32 shp_2_per_addr; 36*4882a593Smuzhiyun s32 shp_2_mcu_addr; 37*4882a593Smuzhiyun s32 mshc_2_mcu_addr; 38*4882a593Smuzhiyun s32 mcu_2_mshc_addr; 39*4882a593Smuzhiyun s32 spdif_2_mcu_addr; 40*4882a593Smuzhiyun s32 mcu_2_spdif_addr; 41*4882a593Smuzhiyun s32 asrc_2_mcu_addr; 42*4882a593Smuzhiyun s32 ext_mem_2_ipu_addr; 43*4882a593Smuzhiyun s32 descrambler_addr; 44*4882a593Smuzhiyun s32 dptc_dvfs_addr; 45*4882a593Smuzhiyun s32 utra_addr; 46*4882a593Smuzhiyun s32 ram_code_start_addr; 47*4882a593Smuzhiyun /* End of v1 array */ 48*4882a593Smuzhiyun s32 mcu_2_ssish_addr; 49*4882a593Smuzhiyun s32 ssish_2_mcu_addr; 50*4882a593Smuzhiyun s32 hdmi_dma_addr; 51*4882a593Smuzhiyun /* End of v2 array */ 52*4882a593Smuzhiyun s32 zcanfd_2_mcu_addr; 53*4882a593Smuzhiyun s32 zqspi_2_mcu_addr; 54*4882a593Smuzhiyun s32 mcu_2_ecspi_addr; 55*4882a593Smuzhiyun /* End of v3 array */ 56*4882a593Smuzhiyun s32 mcu_2_zqspi_addr; 57*4882a593Smuzhiyun /* End of v4 array */ 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /** 61*4882a593Smuzhiyun * struct sdma_platform_data - platform specific data for SDMA engine 62*4882a593Smuzhiyun * 63*4882a593Smuzhiyun * @fw_name The firmware name 64*4882a593Smuzhiyun * @script_addrs SDMA scripts addresses in SDMA ROM 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun struct sdma_platform_data { 67*4882a593Smuzhiyun char *fw_name; 68*4882a593Smuzhiyun struct sdma_script_start_addrs *script_addrs; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif /* __MACH_MXC_SDMA_H__ */ 72