1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for the Synopsys DesignWare DMA Controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Atmel Corporation 6*4882a593Smuzhiyun * Copyright (C) 2010-2011 ST Microelectronics 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _PLATFORM_DATA_DMA_DW_H 9*4882a593Smuzhiyun #define _PLATFORM_DATA_DMA_DW_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/bits.h> 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define DW_DMA_MAX_NR_MASTERS 4 15*4882a593Smuzhiyun #define DW_DMA_MAX_NR_CHANNELS 8 16*4882a593Smuzhiyun #define DW_DMA_MIN_BURST 1 17*4882a593Smuzhiyun #define DW_DMA_MAX_BURST 256 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct device; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /** 22*4882a593Smuzhiyun * struct dw_dma_slave - Controller-specific information about a slave 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * @dma_dev: required DMA master device 25*4882a593Smuzhiyun * @src_id: src request line 26*4882a593Smuzhiyun * @dst_id: dst request line 27*4882a593Smuzhiyun * @m_master: memory master for transfers on allocated channel 28*4882a593Smuzhiyun * @p_master: peripheral master for transfers on allocated channel 29*4882a593Smuzhiyun * @channels: mask of the channels permitted for allocation (zero value means any) 30*4882a593Smuzhiyun * @hs_polarity:set active low polarity of handshake interface 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun struct dw_dma_slave { 33*4882a593Smuzhiyun struct device *dma_dev; 34*4882a593Smuzhiyun u8 src_id; 35*4882a593Smuzhiyun u8 dst_id; 36*4882a593Smuzhiyun u8 m_master; 37*4882a593Smuzhiyun u8 p_master; 38*4882a593Smuzhiyun u8 channels; 39*4882a593Smuzhiyun bool hs_polarity; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /** 43*4882a593Smuzhiyun * struct dw_dma_platform_data - Controller configuration parameters 44*4882a593Smuzhiyun * @nr_channels: Number of channels supported by hardware (max 8) 45*4882a593Smuzhiyun * @chan_allocation_order: Allocate channels starting from 0 or 7 46*4882a593Smuzhiyun * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. 47*4882a593Smuzhiyun * @block_size: Maximum block size supported by the controller 48*4882a593Smuzhiyun * @nr_masters: Number of AHB masters supported by the controller 49*4882a593Smuzhiyun * @data_width: Maximum data width supported by hardware per AHB master 50*4882a593Smuzhiyun * (in bytes, power of 2) 51*4882a593Smuzhiyun * @multi_block: Multi block transfers supported by hardware per channel. 52*4882a593Smuzhiyun * @max_burst: Maximum value of burst transaction size supported by hardware 53*4882a593Smuzhiyun * per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH). 54*4882a593Smuzhiyun * @protctl: Protection control signals setting per channel. 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun struct dw_dma_platform_data { 57*4882a593Smuzhiyun unsigned int nr_channels; 58*4882a593Smuzhiyun #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 59*4882a593Smuzhiyun #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 60*4882a593Smuzhiyun unsigned char chan_allocation_order; 61*4882a593Smuzhiyun #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 62*4882a593Smuzhiyun #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 63*4882a593Smuzhiyun unsigned char chan_priority; 64*4882a593Smuzhiyun unsigned int block_size; 65*4882a593Smuzhiyun unsigned char nr_masters; 66*4882a593Smuzhiyun unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; 67*4882a593Smuzhiyun unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS]; 68*4882a593Smuzhiyun u32 max_burst[DW_DMA_MAX_NR_CHANNELS]; 69*4882a593Smuzhiyun #define CHAN_PROTCTL_PRIVILEGED BIT(0) 70*4882a593Smuzhiyun #define CHAN_PROTCTL_BUFFERABLE BIT(1) 71*4882a593Smuzhiyun #define CHAN_PROTCTL_CACHEABLE BIT(2) 72*4882a593Smuzhiyun #define CHAN_PROTCTL_MASK GENMASK(2, 0) 73*4882a593Smuzhiyun unsigned char protctl; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* _PLATFORM_DATA_DMA_DW_H */ 77