1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Platform data for the COH901318 DMA controller 4*4882a593Smuzhiyun * Copyright (C) 2007-2013 ST-Ericsson 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef PLAT_COH901318_H 8*4882a593Smuzhiyun #define PLAT_COH901318_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifdef CONFIG_COH901318 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* We only support the U300 DMA channels */ 13*4882a593Smuzhiyun #define U300_DMA_MSL_TX_0 0 14*4882a593Smuzhiyun #define U300_DMA_MSL_TX_1 1 15*4882a593Smuzhiyun #define U300_DMA_MSL_TX_2 2 16*4882a593Smuzhiyun #define U300_DMA_MSL_TX_3 3 17*4882a593Smuzhiyun #define U300_DMA_MSL_TX_4 4 18*4882a593Smuzhiyun #define U300_DMA_MSL_TX_5 5 19*4882a593Smuzhiyun #define U300_DMA_MSL_TX_6 6 20*4882a593Smuzhiyun #define U300_DMA_MSL_RX_0 7 21*4882a593Smuzhiyun #define U300_DMA_MSL_RX_1 8 22*4882a593Smuzhiyun #define U300_DMA_MSL_RX_2 9 23*4882a593Smuzhiyun #define U300_DMA_MSL_RX_3 10 24*4882a593Smuzhiyun #define U300_DMA_MSL_RX_4 11 25*4882a593Smuzhiyun #define U300_DMA_MSL_RX_5 12 26*4882a593Smuzhiyun #define U300_DMA_MSL_RX_6 13 27*4882a593Smuzhiyun #define U300_DMA_MMCSD_RX_TX 14 28*4882a593Smuzhiyun #define U300_DMA_MSPRO_TX 15 29*4882a593Smuzhiyun #define U300_DMA_MSPRO_RX 16 30*4882a593Smuzhiyun #define U300_DMA_UART0_TX 17 31*4882a593Smuzhiyun #define U300_DMA_UART0_RX 18 32*4882a593Smuzhiyun #define U300_DMA_APEX_TX 19 33*4882a593Smuzhiyun #define U300_DMA_APEX_RX 20 34*4882a593Smuzhiyun #define U300_DMA_PCM_I2S0_TX 21 35*4882a593Smuzhiyun #define U300_DMA_PCM_I2S0_RX 22 36*4882a593Smuzhiyun #define U300_DMA_PCM_I2S1_TX 23 37*4882a593Smuzhiyun #define U300_DMA_PCM_I2S1_RX 24 38*4882a593Smuzhiyun #define U300_DMA_XGAM_CDI 25 39*4882a593Smuzhiyun #define U300_DMA_XGAM_PDI 26 40*4882a593Smuzhiyun #define U300_DMA_SPI_TX 27 41*4882a593Smuzhiyun #define U300_DMA_SPI_RX 28 42*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_0 29 43*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_1 30 44*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_2 31 45*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_3 32 46*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_4 33 47*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_5 34 48*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_6 35 49*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_7 36 50*4882a593Smuzhiyun #define U300_DMA_GENERAL_PURPOSE_8 37 51*4882a593Smuzhiyun #define U300_DMA_UART1_TX 38 52*4882a593Smuzhiyun #define U300_DMA_UART1_RX 39 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define U300_DMA_DEVICE_CHANNELS 32 55*4882a593Smuzhiyun #define U300_DMA_CHANNELS 40 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /** 58*4882a593Smuzhiyun * coh901318_filter_id() - DMA channel filter function 59*4882a593Smuzhiyun * @chan: dma channel handle 60*4882a593Smuzhiyun * @chan_id: id of dma channel to be filter out 61*4882a593Smuzhiyun * 62*4882a593Smuzhiyun * In dma_request_channel() it specifies what channel id to be requested 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun bool coh901318_filter_id(struct dma_chan *chan, void *chan_id); 65*4882a593Smuzhiyun #else coh901318_filter_id(struct dma_chan * chan,void * chan_id)66*4882a593Smuzhiyunstatic inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) 67*4882a593Smuzhiyun { 68*4882a593Smuzhiyun return false; 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* PLAT_COH901318_H */ 73