1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header file for the Atmel AHB DMA Controller driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2008 Atmel Corporation 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef AT_HDMAC_H 8*4882a593Smuzhiyun #define AT_HDMAC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/dmaengine.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * struct at_dma_platform_data - Controller configuration parameters 14*4882a593Smuzhiyun * @nr_channels: Number of channels supported by hardware (max 8) 15*4882a593Smuzhiyun * @cap_mask: dma_capability flags supported by the platform 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun struct at_dma_platform_data { 18*4882a593Smuzhiyun unsigned int nr_channels; 19*4882a593Smuzhiyun dma_cap_mask_t cap_mask; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /** 23*4882a593Smuzhiyun * struct at_dma_slave - Controller-specific information about a slave 24*4882a593Smuzhiyun * @dma_dev: required DMA master device 25*4882a593Smuzhiyun * @cfg: Platform-specific initializer for the CFG register 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun struct at_dma_slave { 28*4882a593Smuzhiyun struct device *dma_dev; 29*4882a593Smuzhiyun u32 cfg; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Platform-configurable bits in CFG */ 34*4882a593Smuzhiyun #define ATC_PER_MSB(h) ((0x30U & (h)) >> 4) /* Extract most significant bits of a handshaking identifier */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */ 37*4882a593Smuzhiyun #define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */ 38*4882a593Smuzhiyun #define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */ 39*4882a593Smuzhiyun #define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */ 40*4882a593Smuzhiyun #define ATC_SRC_H2SEL_SW (0x0 << 9) 41*4882a593Smuzhiyun #define ATC_SRC_H2SEL_HW (0x1 << 9) 42*4882a593Smuzhiyun #define ATC_SRC_PER_MSB(h) (ATC_PER_MSB(h) << 10) /* Channel src rq (most significant bits) */ 43*4882a593Smuzhiyun #define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */ 44*4882a593Smuzhiyun #define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */ 45*4882a593Smuzhiyun #define ATC_DST_H2SEL_SW (0x0 << 13) 46*4882a593Smuzhiyun #define ATC_DST_H2SEL_HW (0x1 << 13) 47*4882a593Smuzhiyun #define ATC_DST_PER_MSB(h) (ATC_PER_MSB(h) << 14) /* Channel dst rq (most significant bits) */ 48*4882a593Smuzhiyun #define ATC_SOD (0x1 << 16) /* Stop On Done */ 49*4882a593Smuzhiyun #define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */ 50*4882a593Smuzhiyun #define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */ 51*4882a593Smuzhiyun #define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */ 52*4882a593Smuzhiyun #define ATC_LOCK_IF_L_CHUNK (0x0 << 22) 53*4882a593Smuzhiyun #define ATC_LOCK_IF_L_BUFFER (0x1 << 22) 54*4882a593Smuzhiyun #define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */ 55*4882a593Smuzhiyun #define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */ 56*4882a593Smuzhiyun #define ATC_FIFOCFG_LARGESTBURST (0x0 << 28) 57*4882a593Smuzhiyun #define ATC_FIFOCFG_HALFFIFO (0x1 << 28) 58*4882a593Smuzhiyun #define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* AT_HDMAC_H */ 62