1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * TI DaVinci Audio Serial Port support 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 7*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 8*4882a593Smuzhiyun * published by the Free Software Foundation version 2. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 12*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*4882a593Smuzhiyun * GNU General Public License for more details. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __DAVINCI_ASP_H 17*4882a593Smuzhiyun #define __DAVINCI_ASP_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include <linux/genalloc.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct davinci_mcasp_pdata { 22*4882a593Smuzhiyun u32 tx_dma_offset; 23*4882a593Smuzhiyun u32 rx_dma_offset; 24*4882a593Smuzhiyun int asp_chan_q; /* event queue number for ASP channel */ 25*4882a593Smuzhiyun int ram_chan_q; /* event queue number for RAM channel */ 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Allowing this is more efficient and eliminates left and right swaps 28*4882a593Smuzhiyun * caused by underruns, but will swap the left and right channels 29*4882a593Smuzhiyun * when compared to previous behavior. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun unsigned enable_channel_combine:1; 32*4882a593Smuzhiyun unsigned sram_size_playback; 33*4882a593Smuzhiyun unsigned sram_size_capture; 34*4882a593Smuzhiyun struct gen_pool *sram_pool; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * If McBSP peripheral gets the clock from an external pin, 38*4882a593Smuzhiyun * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR 39*4882a593Smuzhiyun * and MCBSP_CLKS. 40*4882a593Smuzhiyun * Depending on different hardware connections it is possible 41*4882a593Smuzhiyun * to use this setting to change the behaviour of McBSP 42*4882a593Smuzhiyun * driver. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun int clk_input_pin; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * This flag works when both clock and FS are outputs for the cpu 48*4882a593Smuzhiyun * and makes clock more accurate (FS is not symmetrical and the 49*4882a593Smuzhiyun * clock is very fast. 50*4882a593Smuzhiyun * The clock becoming faster is named 51*4882a593Smuzhiyun * i2s continuous serial clock (I2S_SCK) and it is an externally 52*4882a593Smuzhiyun * visible bit clock. 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * first line : WordSelect 55*4882a593Smuzhiyun * second line : ContinuousSerialClock 56*4882a593Smuzhiyun * third line: SerialData 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun * SYMMETRICAL APPROACH: 59*4882a593Smuzhiyun * _______________________ LEFT 60*4882a593Smuzhiyun * _| RIGHT |______________________| 61*4882a593Smuzhiyun * _ _ _ _ _ _ _ _ 62*4882a593Smuzhiyun * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ 63*4882a593Smuzhiyun * _ _ _ _ _ _ _ _ 64*4882a593Smuzhiyun * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ 65*4882a593Smuzhiyun * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * ACCURATE CLOCK APPROACH: 68*4882a593Smuzhiyun * ______________ LEFT 69*4882a593Smuzhiyun * _| RIGHT |_______________________________| 70*4882a593Smuzhiyun * _ _ _ _ _ _ _ _ _ 71*4882a593Smuzhiyun * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | 72*4882a593Smuzhiyun * _ _ _ _ dummy cycles 73*4882a593Smuzhiyun * _/ \_ ... _/ \_/ \_ ... _/ \__________________ 74*4882a593Smuzhiyun * \_/ \_/ \_/ \_/ 75*4882a593Smuzhiyun * 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun bool i2s_accurate_sck; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* McASP specific fields */ 80*4882a593Smuzhiyun int tdm_slots; 81*4882a593Smuzhiyun u8 op_mode; 82*4882a593Smuzhiyun u8 dismod; 83*4882a593Smuzhiyun u8 num_serializer; 84*4882a593Smuzhiyun u8 *serial_dir; 85*4882a593Smuzhiyun u8 version; 86*4882a593Smuzhiyun u8 txnumevt; 87*4882a593Smuzhiyun u8 rxnumevt; 88*4882a593Smuzhiyun int tx_dma_channel; 89*4882a593Smuzhiyun int rx_dma_channel; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun /* TODO: Fix arch/arm/mach-davinci/ users and remove this define */ 92*4882a593Smuzhiyun #define snd_platform_data davinci_mcasp_pdata 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun enum { 95*4882a593Smuzhiyun MCASP_VERSION_1 = 0, /* DM646x */ 96*4882a593Smuzhiyun MCASP_VERSION_2, /* DA8xx/OMAPL1x */ 97*4882a593Smuzhiyun MCASP_VERSION_3, /* TI81xx/AM33xx */ 98*4882a593Smuzhiyun MCASP_VERSION_4, /* DRA7xxx */ 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun enum mcbsp_clk_input_pin { 102*4882a593Smuzhiyun MCBSP_CLKR = 0, /* as in DM365 */ 103*4882a593Smuzhiyun MCBSP_CLKS, 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define INACTIVE_MODE 0 107*4882a593Smuzhiyun #define TX_MODE 1 108*4882a593Smuzhiyun #define RX_MODE 2 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define DAVINCI_MCASP_IIS_MODE 0 111*4882a593Smuzhiyun #define DAVINCI_MCASP_DIT_MODE 1 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif 114