1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Analog Devices ADP5588 I/O Expander and QWERTY Keypad Controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009-2010 Analog Devices Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ADP5588_H 9*4882a593Smuzhiyun #define _ADP5588_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define DEV_ID 0x00 /* Device ID */ 12*4882a593Smuzhiyun #define CFG 0x01 /* Configuration Register1 */ 13*4882a593Smuzhiyun #define INT_STAT 0x02 /* Interrupt Status Register */ 14*4882a593Smuzhiyun #define KEY_LCK_EC_STAT 0x03 /* Key Lock and Event Counter Register */ 15*4882a593Smuzhiyun #define Key_EVENTA 0x04 /* Key Event Register A */ 16*4882a593Smuzhiyun #define Key_EVENTB 0x05 /* Key Event Register B */ 17*4882a593Smuzhiyun #define Key_EVENTC 0x06 /* Key Event Register C */ 18*4882a593Smuzhiyun #define Key_EVENTD 0x07 /* Key Event Register D */ 19*4882a593Smuzhiyun #define Key_EVENTE 0x08 /* Key Event Register E */ 20*4882a593Smuzhiyun #define Key_EVENTF 0x09 /* Key Event Register F */ 21*4882a593Smuzhiyun #define Key_EVENTG 0x0A /* Key Event Register G */ 22*4882a593Smuzhiyun #define Key_EVENTH 0x0B /* Key Event Register H */ 23*4882a593Smuzhiyun #define Key_EVENTI 0x0C /* Key Event Register I */ 24*4882a593Smuzhiyun #define Key_EVENTJ 0x0D /* Key Event Register J */ 25*4882a593Smuzhiyun #define KP_LCK_TMR 0x0E /* Keypad Lock1 to Lock2 Timer */ 26*4882a593Smuzhiyun #define UNLOCK1 0x0F /* Unlock Key1 */ 27*4882a593Smuzhiyun #define UNLOCK2 0x10 /* Unlock Key2 */ 28*4882a593Smuzhiyun #define GPIO_INT_STAT1 0x11 /* GPIO Interrupt Status */ 29*4882a593Smuzhiyun #define GPIO_INT_STAT2 0x12 /* GPIO Interrupt Status */ 30*4882a593Smuzhiyun #define GPIO_INT_STAT3 0x13 /* GPIO Interrupt Status */ 31*4882a593Smuzhiyun #define GPIO_DAT_STAT1 0x14 /* GPIO Data Status, Read twice to clear */ 32*4882a593Smuzhiyun #define GPIO_DAT_STAT2 0x15 /* GPIO Data Status, Read twice to clear */ 33*4882a593Smuzhiyun #define GPIO_DAT_STAT3 0x16 /* GPIO Data Status, Read twice to clear */ 34*4882a593Smuzhiyun #define GPIO_DAT_OUT1 0x17 /* GPIO DATA OUT */ 35*4882a593Smuzhiyun #define GPIO_DAT_OUT2 0x18 /* GPIO DATA OUT */ 36*4882a593Smuzhiyun #define GPIO_DAT_OUT3 0x19 /* GPIO DATA OUT */ 37*4882a593Smuzhiyun #define GPIO_INT_EN1 0x1A /* GPIO Interrupt Enable */ 38*4882a593Smuzhiyun #define GPIO_INT_EN2 0x1B /* GPIO Interrupt Enable */ 39*4882a593Smuzhiyun #define GPIO_INT_EN3 0x1C /* GPIO Interrupt Enable */ 40*4882a593Smuzhiyun #define KP_GPIO1 0x1D /* Keypad or GPIO Selection */ 41*4882a593Smuzhiyun #define KP_GPIO2 0x1E /* Keypad or GPIO Selection */ 42*4882a593Smuzhiyun #define KP_GPIO3 0x1F /* Keypad or GPIO Selection */ 43*4882a593Smuzhiyun #define GPI_EM1 0x20 /* GPI Event Mode 1 */ 44*4882a593Smuzhiyun #define GPI_EM2 0x21 /* GPI Event Mode 2 */ 45*4882a593Smuzhiyun #define GPI_EM3 0x22 /* GPI Event Mode 3 */ 46*4882a593Smuzhiyun #define GPIO_DIR1 0x23 /* GPIO Data Direction */ 47*4882a593Smuzhiyun #define GPIO_DIR2 0x24 /* GPIO Data Direction */ 48*4882a593Smuzhiyun #define GPIO_DIR3 0x25 /* GPIO Data Direction */ 49*4882a593Smuzhiyun #define GPIO_INT_LVL1 0x26 /* GPIO Edge/Level Detect */ 50*4882a593Smuzhiyun #define GPIO_INT_LVL2 0x27 /* GPIO Edge/Level Detect */ 51*4882a593Smuzhiyun #define GPIO_INT_LVL3 0x28 /* GPIO Edge/Level Detect */ 52*4882a593Smuzhiyun #define Debounce_DIS1 0x29 /* Debounce Disable */ 53*4882a593Smuzhiyun #define Debounce_DIS2 0x2A /* Debounce Disable */ 54*4882a593Smuzhiyun #define Debounce_DIS3 0x2B /* Debounce Disable */ 55*4882a593Smuzhiyun #define GPIO_PULL1 0x2C /* GPIO Pull Disable */ 56*4882a593Smuzhiyun #define GPIO_PULL2 0x2D /* GPIO Pull Disable */ 57*4882a593Smuzhiyun #define GPIO_PULL3 0x2E /* GPIO Pull Disable */ 58*4882a593Smuzhiyun #define CMP_CFG_STAT 0x30 /* Comparator Configuration and Status Register */ 59*4882a593Smuzhiyun #define CMP_CONFG_SENS1 0x31 /* Sensor1 Comparator Configuration Register */ 60*4882a593Smuzhiyun #define CMP_CONFG_SENS2 0x32 /* L2 Light Sensor Reference Level, Output Falling for Sensor 1 */ 61*4882a593Smuzhiyun #define CMP1_LVL2_TRIP 0x33 /* L2 Light Sensor Hysteresis (Active when Output Rising) for Sensor 1 */ 62*4882a593Smuzhiyun #define CMP1_LVL2_HYS 0x34 /* L3 Light Sensor Reference Level, Output Falling For Sensor 1 */ 63*4882a593Smuzhiyun #define CMP1_LVL3_TRIP 0x35 /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 1 */ 64*4882a593Smuzhiyun #define CMP1_LVL3_HYS 0x36 /* Sensor 2 Comparator Configuration Register */ 65*4882a593Smuzhiyun #define CMP2_LVL2_TRIP 0x37 /* L2 Light Sensor Reference Level, Output Falling for Sensor 2 */ 66*4882a593Smuzhiyun #define CMP2_LVL2_HYS 0x38 /* L2 Light Sensor Hysteresis (Active when Output Rising) for Sensor 2 */ 67*4882a593Smuzhiyun #define CMP2_LVL3_TRIP 0x39 /* L3 Light Sensor Reference Level, Output Falling For Sensor 2 */ 68*4882a593Smuzhiyun #define CMP2_LVL3_HYS 0x3A /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 2 */ 69*4882a593Smuzhiyun #define CMP1_ADC_DAT_R1 0x3B /* Comparator 1 ADC data Register1 */ 70*4882a593Smuzhiyun #define CMP1_ADC_DAT_R2 0x3C /* Comparator 1 ADC data Register2 */ 71*4882a593Smuzhiyun #define CMP2_ADC_DAT_R1 0x3D /* Comparator 2 ADC data Register1 */ 72*4882a593Smuzhiyun #define CMP2_ADC_DAT_R2 0x3E /* Comparator 2 ADC data Register2 */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define ADP5588_DEVICE_ID_MASK 0xF 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Configuration Register1 */ 77*4882a593Smuzhiyun #define ADP5588_AUTO_INC (1 << 7) 78*4882a593Smuzhiyun #define ADP5588_GPIEM_CFG (1 << 6) 79*4882a593Smuzhiyun #define ADP5588_OVR_FLOW_M (1 << 5) 80*4882a593Smuzhiyun #define ADP5588_INT_CFG (1 << 4) 81*4882a593Smuzhiyun #define ADP5588_OVR_FLOW_IEN (1 << 3) 82*4882a593Smuzhiyun #define ADP5588_K_LCK_IM (1 << 2) 83*4882a593Smuzhiyun #define ADP5588_GPI_IEN (1 << 1) 84*4882a593Smuzhiyun #define ADP5588_KE_IEN (1 << 0) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Interrupt Status Register */ 87*4882a593Smuzhiyun #define ADP5588_CMP2_INT (1 << 5) 88*4882a593Smuzhiyun #define ADP5588_CMP1_INT (1 << 4) 89*4882a593Smuzhiyun #define ADP5588_OVR_FLOW_INT (1 << 3) 90*4882a593Smuzhiyun #define ADP5588_K_LCK_INT (1 << 2) 91*4882a593Smuzhiyun #define ADP5588_GPI_INT (1 << 1) 92*4882a593Smuzhiyun #define ADP5588_KE_INT (1 << 0) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Key Lock and Event Counter Register */ 95*4882a593Smuzhiyun #define ADP5588_K_LCK_EN (1 << 6) 96*4882a593Smuzhiyun #define ADP5588_LCK21 0x30 97*4882a593Smuzhiyun #define ADP5588_KEC 0xF 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define ADP5588_MAXGPIO 18 100*4882a593Smuzhiyun #define ADP5588_BANK(offs) ((offs) >> 3) 101*4882a593Smuzhiyun #define ADP5588_BIT(offs) (1u << ((offs) & 0x7)) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Put one of these structures in i2c_board_info platform_data */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define ADP5588_KEYMAPSIZE 80 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define GPI_PIN_ROW0 97 108*4882a593Smuzhiyun #define GPI_PIN_ROW1 98 109*4882a593Smuzhiyun #define GPI_PIN_ROW2 99 110*4882a593Smuzhiyun #define GPI_PIN_ROW3 100 111*4882a593Smuzhiyun #define GPI_PIN_ROW4 101 112*4882a593Smuzhiyun #define GPI_PIN_ROW5 102 113*4882a593Smuzhiyun #define GPI_PIN_ROW6 103 114*4882a593Smuzhiyun #define GPI_PIN_ROW7 104 115*4882a593Smuzhiyun #define GPI_PIN_COL0 105 116*4882a593Smuzhiyun #define GPI_PIN_COL1 106 117*4882a593Smuzhiyun #define GPI_PIN_COL2 107 118*4882a593Smuzhiyun #define GPI_PIN_COL3 108 119*4882a593Smuzhiyun #define GPI_PIN_COL4 109 120*4882a593Smuzhiyun #define GPI_PIN_COL5 110 121*4882a593Smuzhiyun #define GPI_PIN_COL6 111 122*4882a593Smuzhiyun #define GPI_PIN_COL7 112 123*4882a593Smuzhiyun #define GPI_PIN_COL8 113 124*4882a593Smuzhiyun #define GPI_PIN_COL9 114 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define GPI_PIN_ROW_BASE GPI_PIN_ROW0 127*4882a593Smuzhiyun #define GPI_PIN_ROW_END GPI_PIN_ROW7 128*4882a593Smuzhiyun #define GPI_PIN_COL_BASE GPI_PIN_COL0 129*4882a593Smuzhiyun #define GPI_PIN_COL_END GPI_PIN_COL9 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define GPI_PIN_BASE GPI_PIN_ROW_BASE 132*4882a593Smuzhiyun #define GPI_PIN_END GPI_PIN_COL_END 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define ADP5588_GPIMAPSIZE_MAX (GPI_PIN_END - GPI_PIN_BASE + 1) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun struct adp5588_gpi_map { 137*4882a593Smuzhiyun unsigned short pin; 138*4882a593Smuzhiyun unsigned short sw_evt; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun struct adp5588_kpad_platform_data { 142*4882a593Smuzhiyun int rows; /* Number of rows */ 143*4882a593Smuzhiyun int cols; /* Number of columns */ 144*4882a593Smuzhiyun const unsigned short *keymap; /* Pointer to keymap */ 145*4882a593Smuzhiyun unsigned short keymapsize; /* Keymap size */ 146*4882a593Smuzhiyun unsigned repeat:1; /* Enable key repeat */ 147*4882a593Smuzhiyun unsigned en_keylock:1; /* Enable Key Lock feature */ 148*4882a593Smuzhiyun unsigned short unlock_key1; /* Unlock Key 1 */ 149*4882a593Smuzhiyun unsigned short unlock_key2; /* Unlock Key 2 */ 150*4882a593Smuzhiyun const struct adp5588_gpi_map *gpimap; 151*4882a593Smuzhiyun unsigned short gpimapsize; 152*4882a593Smuzhiyun const struct adp5588_gpio_platform_data *gpio_data; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun struct i2c_client; /* forward declaration */ 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun struct adp5588_gpio_platform_data { 158*4882a593Smuzhiyun int gpio_start; /* GPIO Chip base # */ 159*4882a593Smuzhiyun const char *const *names; 160*4882a593Smuzhiyun unsigned irq_base; /* interrupt base # */ 161*4882a593Smuzhiyun unsigned pullup_dis_mask; /* Pull-Up Disable Mask */ 162*4882a593Smuzhiyun int (*setup)(struct i2c_client *client, 163*4882a593Smuzhiyun unsigned gpio, unsigned ngpio, 164*4882a593Smuzhiyun void *context); 165*4882a593Smuzhiyun int (*teardown)(struct i2c_client *client, 166*4882a593Smuzhiyun unsigned gpio, unsigned ngpio, 167*4882a593Smuzhiyun void *context); 168*4882a593Smuzhiyun void *context; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #endif 172