1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2012 Analog Devices Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __LINUX_PLATFORM_DATA_AD5755_H__ 6*4882a593Smuzhiyun #define __LINUX_PLATFORM_DATA_AD5755_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun enum ad5755_mode { 9*4882a593Smuzhiyun AD5755_MODE_VOLTAGE_0V_5V = 0, 10*4882a593Smuzhiyun AD5755_MODE_VOLTAGE_0V_10V = 1, 11*4882a593Smuzhiyun AD5755_MODE_VOLTAGE_PLUSMINUS_5V = 2, 12*4882a593Smuzhiyun AD5755_MODE_VOLTAGE_PLUSMINUS_10V = 3, 13*4882a593Smuzhiyun AD5755_MODE_CURRENT_4mA_20mA = 4, 14*4882a593Smuzhiyun AD5755_MODE_CURRENT_0mA_20mA = 5, 15*4882a593Smuzhiyun AD5755_MODE_CURRENT_0mA_24mA = 6, 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun enum ad5755_dc_dc_phase { 19*4882a593Smuzhiyun AD5755_DC_DC_PHASE_ALL_SAME_EDGE = 0, 20*4882a593Smuzhiyun AD5755_DC_DC_PHASE_A_B_SAME_EDGE_C_D_OPP_EDGE = 1, 21*4882a593Smuzhiyun AD5755_DC_DC_PHASE_A_C_SAME_EDGE_B_D_OPP_EDGE = 2, 22*4882a593Smuzhiyun AD5755_DC_DC_PHASE_90_DEGREE = 3, 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum ad5755_dc_dc_freq { 26*4882a593Smuzhiyun AD5755_DC_DC_FREQ_250kHZ = 0, 27*4882a593Smuzhiyun AD5755_DC_DC_FREQ_410kHZ = 1, 28*4882a593Smuzhiyun AD5755_DC_DC_FREQ_650kHZ = 2, 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum ad5755_dc_dc_maxv { 32*4882a593Smuzhiyun AD5755_DC_DC_MAXV_23V = 0, 33*4882a593Smuzhiyun AD5755_DC_DC_MAXV_24V5 = 1, 34*4882a593Smuzhiyun AD5755_DC_DC_MAXV_27V = 2, 35*4882a593Smuzhiyun AD5755_DC_DC_MAXV_29V5 = 3, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun enum ad5755_slew_rate { 39*4882a593Smuzhiyun AD5755_SLEW_RATE_64k = 0, 40*4882a593Smuzhiyun AD5755_SLEW_RATE_32k = 1, 41*4882a593Smuzhiyun AD5755_SLEW_RATE_16k = 2, 42*4882a593Smuzhiyun AD5755_SLEW_RATE_8k = 3, 43*4882a593Smuzhiyun AD5755_SLEW_RATE_4k = 4, 44*4882a593Smuzhiyun AD5755_SLEW_RATE_2k = 5, 45*4882a593Smuzhiyun AD5755_SLEW_RATE_1k = 6, 46*4882a593Smuzhiyun AD5755_SLEW_RATE_500 = 7, 47*4882a593Smuzhiyun AD5755_SLEW_RATE_250 = 8, 48*4882a593Smuzhiyun AD5755_SLEW_RATE_125 = 9, 49*4882a593Smuzhiyun AD5755_SLEW_RATE_64 = 10, 50*4882a593Smuzhiyun AD5755_SLEW_RATE_32 = 11, 51*4882a593Smuzhiyun AD5755_SLEW_RATE_16 = 12, 52*4882a593Smuzhiyun AD5755_SLEW_RATE_8 = 13, 53*4882a593Smuzhiyun AD5755_SLEW_RATE_4 = 14, 54*4882a593Smuzhiyun AD5755_SLEW_RATE_0_5 = 15, 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun enum ad5755_slew_step_size { 58*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_1 = 0, 59*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_2 = 1, 60*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_4 = 2, 61*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_8 = 3, 62*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_16 = 4, 63*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_32 = 5, 64*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_64 = 6, 65*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_128 = 7, 66*4882a593Smuzhiyun AD5755_SLEW_STEP_SIZE_256 = 8, 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /** 70*4882a593Smuzhiyun * struct ad5755_platform_data - AD5755 DAC driver platform data 71*4882a593Smuzhiyun * @ext_dc_dc_compenstation_resistor: Whether an external DC-DC converter 72*4882a593Smuzhiyun * compensation register is used. 73*4882a593Smuzhiyun * @dc_dc_phase: DC-DC converter phase. 74*4882a593Smuzhiyun * @dc_dc_freq: DC-DC converter frequency. 75*4882a593Smuzhiyun * @dc_dc_maxv: DC-DC maximum allowed boost voltage. 76*4882a593Smuzhiyun * @dac.mode: The mode to be used for the DAC output. 77*4882a593Smuzhiyun * @dac.ext_current_sense_resistor: Whether an external current sense resistor 78*4882a593Smuzhiyun * is used. 79*4882a593Smuzhiyun * @dac.enable_voltage_overrange: Whether to enable 20% voltage output overrange. 80*4882a593Smuzhiyun * @dac.slew.enable: Whether to enable digital slew. 81*4882a593Smuzhiyun * @dac.slew.rate: Slew rate of the digital slew. 82*4882a593Smuzhiyun * @dac.slew.step_size: Slew step size of the digital slew. 83*4882a593Smuzhiyun **/ 84*4882a593Smuzhiyun struct ad5755_platform_data { 85*4882a593Smuzhiyun bool ext_dc_dc_compenstation_resistor; 86*4882a593Smuzhiyun enum ad5755_dc_dc_phase dc_dc_phase; 87*4882a593Smuzhiyun enum ad5755_dc_dc_freq dc_dc_freq; 88*4882a593Smuzhiyun enum ad5755_dc_dc_maxv dc_dc_maxv; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct { 91*4882a593Smuzhiyun enum ad5755_mode mode; 92*4882a593Smuzhiyun bool ext_current_sense_resistor; 93*4882a593Smuzhiyun bool enable_voltage_overrange; 94*4882a593Smuzhiyun struct { 95*4882a593Smuzhiyun bool enable; 96*4882a593Smuzhiyun enum ad5755_slew_rate rate; 97*4882a593Smuzhiyun enum ad5755_slew_step_size step_size; 98*4882a593Smuzhiyun } slew; 99*4882a593Smuzhiyun } dac[4]; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif 103