xref: /OK3568_Linux_fs/kernel/include/linux/pinctrl/pinctrl.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Interface the pinctrl subsystem
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2011 ST-Ericsson SA
6*4882a593Smuzhiyun  * Written on behalf of Linaro for ST-Ericsson
7*4882a593Smuzhiyun  * This interface is used in the core to keep track of pins.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Author: Linus Walleij <linus.walleij@linaro.org>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #ifndef __LINUX_PINCTRL_PINCTRL_H
12*4882a593Smuzhiyun #define __LINUX_PINCTRL_PINCTRL_H
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/radix-tree.h>
15*4882a593Smuzhiyun #include <linux/list.h>
16*4882a593Smuzhiyun #include <linux/seq_file.h>
17*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl-state.h>
18*4882a593Smuzhiyun #include <linux/pinctrl/devinfo.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun struct device;
21*4882a593Smuzhiyun struct pinctrl_dev;
22*4882a593Smuzhiyun struct pinctrl_map;
23*4882a593Smuzhiyun struct pinmux_ops;
24*4882a593Smuzhiyun struct pinconf_ops;
25*4882a593Smuzhiyun struct pin_config_item;
26*4882a593Smuzhiyun struct gpio_chip;
27*4882a593Smuzhiyun struct device_node;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /**
30*4882a593Smuzhiyun  * struct pinctrl_pin_desc - boards/machines provide information on their
31*4882a593Smuzhiyun  * pins, pads or other muxable units in this struct
32*4882a593Smuzhiyun  * @number: unique pin number from the global pin number space
33*4882a593Smuzhiyun  * @name: a name for this pin
34*4882a593Smuzhiyun  * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
35*4882a593Smuzhiyun  */
36*4882a593Smuzhiyun struct pinctrl_pin_desc {
37*4882a593Smuzhiyun 	unsigned number;
38*4882a593Smuzhiyun 	const char *name;
39*4882a593Smuzhiyun 	void *drv_data;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* Convenience macro to define a single named or anonymous pin descriptor */
43*4882a593Smuzhiyun #define PINCTRL_PIN(a, b) { .number = a, .name = b }
44*4882a593Smuzhiyun #define PINCTRL_PIN_ANON(a) { .number = a }
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /**
47*4882a593Smuzhiyun  * struct pinctrl_gpio_range - each pin controller can provide subranges of
48*4882a593Smuzhiyun  * the GPIO number space to be handled by the controller
49*4882a593Smuzhiyun  * @node: list node for internal use
50*4882a593Smuzhiyun  * @name: a name for the chip in this range
51*4882a593Smuzhiyun  * @id: an ID number for the chip in this range
52*4882a593Smuzhiyun  * @base: base offset of the GPIO range
53*4882a593Smuzhiyun  * @pin_base: base pin number of the GPIO range if pins == NULL
54*4882a593Smuzhiyun  * @pins: enumeration of pins in GPIO range or NULL
55*4882a593Smuzhiyun  * @npins: number of pins in the GPIO range, including the base number
56*4882a593Smuzhiyun  * @gc: an optional pointer to a gpio_chip
57*4882a593Smuzhiyun  */
58*4882a593Smuzhiyun struct pinctrl_gpio_range {
59*4882a593Smuzhiyun 	struct list_head node;
60*4882a593Smuzhiyun 	const char *name;
61*4882a593Smuzhiyun 	unsigned int id;
62*4882a593Smuzhiyun 	unsigned int base;
63*4882a593Smuzhiyun 	unsigned int pin_base;
64*4882a593Smuzhiyun 	unsigned const *pins;
65*4882a593Smuzhiyun 	unsigned int npins;
66*4882a593Smuzhiyun 	struct gpio_chip *gc;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /**
70*4882a593Smuzhiyun  * struct pinctrl_ops - global pin control operations, to be implemented by
71*4882a593Smuzhiyun  * pin controller drivers.
72*4882a593Smuzhiyun  * @get_groups_count: Returns the count of total number of groups registered.
73*4882a593Smuzhiyun  * @get_group_name: return the group name of the pin group
74*4882a593Smuzhiyun  * @get_group_pins: return an array of pins corresponding to a certain
75*4882a593Smuzhiyun  *	group selector @pins, and the size of the array in @num_pins
76*4882a593Smuzhiyun  * @pin_dbg_show: optional debugfs display hook that will provide per-device
77*4882a593Smuzhiyun  *	info for a certain pin in debugfs
78*4882a593Smuzhiyun  * @dt_node_to_map: parse a device tree "pin configuration node", and create
79*4882a593Smuzhiyun  *	mapping table entries for it. These are returned through the @map and
80*4882a593Smuzhiyun  *	@num_maps output parameters. This function is optional, and may be
81*4882a593Smuzhiyun  *	omitted for pinctrl drivers that do not support device tree.
82*4882a593Smuzhiyun  * @dt_free_map: free mapping table entries created via @dt_node_to_map. The
83*4882a593Smuzhiyun  *	top-level @map pointer must be freed, along with any dynamically
84*4882a593Smuzhiyun  *	allocated members of the mapping table entries themselves. This
85*4882a593Smuzhiyun  *	function is optional, and may be omitted for pinctrl drivers that do
86*4882a593Smuzhiyun  *	not support device tree.
87*4882a593Smuzhiyun  */
88*4882a593Smuzhiyun struct pinctrl_ops {
89*4882a593Smuzhiyun 	int (*get_groups_count) (struct pinctrl_dev *pctldev);
90*4882a593Smuzhiyun 	const char *(*get_group_name) (struct pinctrl_dev *pctldev,
91*4882a593Smuzhiyun 				       unsigned selector);
92*4882a593Smuzhiyun 	int (*get_group_pins) (struct pinctrl_dev *pctldev,
93*4882a593Smuzhiyun 			       unsigned selector,
94*4882a593Smuzhiyun 			       const unsigned **pins,
95*4882a593Smuzhiyun 			       unsigned *num_pins);
96*4882a593Smuzhiyun 	void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
97*4882a593Smuzhiyun 			  unsigned offset);
98*4882a593Smuzhiyun 	int (*dt_node_to_map) (struct pinctrl_dev *pctldev,
99*4882a593Smuzhiyun 			       struct device_node *np_config,
100*4882a593Smuzhiyun 			       struct pinctrl_map **map, unsigned *num_maps);
101*4882a593Smuzhiyun 	void (*dt_free_map) (struct pinctrl_dev *pctldev,
102*4882a593Smuzhiyun 			     struct pinctrl_map *map, unsigned num_maps);
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /**
106*4882a593Smuzhiyun  * struct pinctrl_desc - pin controller descriptor, register this to pin
107*4882a593Smuzhiyun  * control subsystem
108*4882a593Smuzhiyun  * @name: name for the pin controller
109*4882a593Smuzhiyun  * @pins: an array of pin descriptors describing all the pins handled by
110*4882a593Smuzhiyun  *	this pin controller
111*4882a593Smuzhiyun  * @npins: number of descriptors in the array, usually just ARRAY_SIZE()
112*4882a593Smuzhiyun  *	of the pins field above
113*4882a593Smuzhiyun  * @pctlops: pin control operation vtable, to support global concepts like
114*4882a593Smuzhiyun  *	grouping of pins, this is optional.
115*4882a593Smuzhiyun  * @pmxops: pinmux operations vtable, if you support pinmuxing in your driver
116*4882a593Smuzhiyun  * @confops: pin config operations vtable, if you support pin configuration in
117*4882a593Smuzhiyun  *	your driver
118*4882a593Smuzhiyun  * @owner: module providing the pin controller, used for refcounting
119*4882a593Smuzhiyun  * @num_custom_params: Number of driver-specific custom parameters to be parsed
120*4882a593Smuzhiyun  *	from the hardware description
121*4882a593Smuzhiyun  * @custom_params: List of driver_specific custom parameters to be parsed from
122*4882a593Smuzhiyun  *	the hardware description
123*4882a593Smuzhiyun  * @custom_conf_items: Information how to print @params in debugfs, must be
124*4882a593Smuzhiyun  *	the same size as the @custom_params, i.e. @num_custom_params
125*4882a593Smuzhiyun  * @link_consumers: If true create a device link between pinctrl and its
126*4882a593Smuzhiyun  *	consumers (i.e. the devices requesting pin control states). This is
127*4882a593Smuzhiyun  *	sometimes necessary to ascertain the right suspend/resume order for
128*4882a593Smuzhiyun  *	example.
129*4882a593Smuzhiyun  */
130*4882a593Smuzhiyun struct pinctrl_desc {
131*4882a593Smuzhiyun 	const char *name;
132*4882a593Smuzhiyun 	const struct pinctrl_pin_desc *pins;
133*4882a593Smuzhiyun 	unsigned int npins;
134*4882a593Smuzhiyun 	const struct pinctrl_ops *pctlops;
135*4882a593Smuzhiyun 	const struct pinmux_ops *pmxops;
136*4882a593Smuzhiyun 	const struct pinconf_ops *confops;
137*4882a593Smuzhiyun 	struct module *owner;
138*4882a593Smuzhiyun #ifdef CONFIG_GENERIC_PINCONF
139*4882a593Smuzhiyun 	unsigned int num_custom_params;
140*4882a593Smuzhiyun 	const struct pinconf_generic_params *custom_params;
141*4882a593Smuzhiyun 	const struct pin_config_item *custom_conf_items;
142*4882a593Smuzhiyun #endif
143*4882a593Smuzhiyun 	bool link_consumers;
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /* External interface to pin controller */
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun extern int pinctrl_register_and_init(struct pinctrl_desc *pctldesc,
149*4882a593Smuzhiyun 				     struct device *dev, void *driver_data,
150*4882a593Smuzhiyun 				     struct pinctrl_dev **pctldev);
151*4882a593Smuzhiyun extern int pinctrl_enable(struct pinctrl_dev *pctldev);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun /* Please use pinctrl_register_and_init() and pinctrl_enable() instead */
154*4882a593Smuzhiyun extern struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
155*4882a593Smuzhiyun 				struct device *dev, void *driver_data);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun extern void pinctrl_unregister(struct pinctrl_dev *pctldev);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun extern int devm_pinctrl_register_and_init(struct device *dev,
160*4882a593Smuzhiyun 				struct pinctrl_desc *pctldesc,
161*4882a593Smuzhiyun 				void *driver_data,
162*4882a593Smuzhiyun 				struct pinctrl_dev **pctldev);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /* Please use devm_pinctrl_register_and_init() instead */
165*4882a593Smuzhiyun extern struct pinctrl_dev *devm_pinctrl_register(struct device *dev,
166*4882a593Smuzhiyun 				struct pinctrl_desc *pctldesc,
167*4882a593Smuzhiyun 				void *driver_data);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun extern void devm_pinctrl_unregister(struct device *dev,
170*4882a593Smuzhiyun 				struct pinctrl_dev *pctldev);
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun extern void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
173*4882a593Smuzhiyun 				struct pinctrl_gpio_range *range);
174*4882a593Smuzhiyun extern void pinctrl_add_gpio_ranges(struct pinctrl_dev *pctldev,
175*4882a593Smuzhiyun 				struct pinctrl_gpio_range *ranges,
176*4882a593Smuzhiyun 				unsigned nranges);
177*4882a593Smuzhiyun extern void pinctrl_remove_gpio_range(struct pinctrl_dev *pctldev,
178*4882a593Smuzhiyun 				struct pinctrl_gpio_range *range);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun extern struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname,
181*4882a593Smuzhiyun 		struct pinctrl_gpio_range *range);
182*4882a593Smuzhiyun extern struct pinctrl_gpio_range *
183*4882a593Smuzhiyun pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
184*4882a593Smuzhiyun 				 unsigned int pin);
185*4882a593Smuzhiyun extern int pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
186*4882a593Smuzhiyun 				const char *pin_group, const unsigned **pins,
187*4882a593Smuzhiyun 				unsigned *num_pins);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PINCTRL)
190*4882a593Smuzhiyun extern struct pinctrl_dev *of_pinctrl_get(struct device_node *np);
191*4882a593Smuzhiyun #else
192*4882a593Smuzhiyun static inline
of_pinctrl_get(struct device_node * np)193*4882a593Smuzhiyun struct pinctrl_dev *of_pinctrl_get(struct device_node *np)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	return NULL;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun #endif /* CONFIG_OF */
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun extern const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev);
200*4882a593Smuzhiyun extern const char *pinctrl_dev_get_devname(struct pinctrl_dev *pctldev);
201*4882a593Smuzhiyun extern void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun #endif /* __LINUX_PINCTRL_PINCTRL_H */
204